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1 of 105 031600 features four e1 (cept or pcm-30) /isdn-pri framing transceivers all four framers are fully independent; transmit and receive sections of each framer are fully independent frames to fas, cas, ccs, and crc4 formats each of the four framers contain dual two? frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192 mhz 8?bit parallel control port that can be used directly on either multiplexed or non? multiplexed buses (intel or motorola) easy access to si and sa bits extracts and inserts cas signaling large counters for bipolar and code violations, crc4 code word errors, fas word errors, and e-bits programmable output clocks for fractional e1, per channel loopback, h0 and h12 applications integral hdlc controller with 64-byte buffers configurable for sa bits or ds0 operation detects and generates ais, remote alarm, and remote multiframe alarms pin compatible with ds21q42 enhanced quad t1 framer 3.3v supply with 5v tolerant i/o; low power cmos available in 128?pin tqfp package ieee 1149.1 support functional diagram recei ve framer elastic store transmit formatter elastic store framer #0 framer #1 framer #2 framer #3 control port actual size quad e1 framer ordering information ds21q44t (0 0 c to 70 0 c) DS21Q44TN (-40 0 c to +85 0 c) description the ds21q44 e1 is an enhanced version of the ds21q43 quad e1 framer. the ds21q44 contains four framers that are configured and read through a common microprocessor compatible parallel port. each framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. all four framers in the ds21q44 are totally independent, they do not share a common framing synchronizer. also the transmit and receive sides of each framer are totally independent. the dual two-frame elastic stores contained in each of the four framers can be independently enabled and disabled as required. the device fully meets all of the latest e1 specifications including ccitt/itu g.704, g.706, g.962, and i.431 as well as ets 300 011 and ets 300 233. ds21q44 enhanced quad e1 framer www.dalsemi.com
ds21q44 2 of 105 1. introduction the ds21q44 is a superset version of the popular ds21q43 quad e1 framer offering the new features listed below. all of the original features of the ds21q43 have been retained and software created for the original device is transferable to the ds21q44. new features additional hardware signaling capability including: ? receive signaling reinsertion to a backplane multiframe sync ? availability of signaling in a separate pcm data stream ? signaling freezing ? interrupt generated on change of signaling data per?channel code insertion in both transmit and receive paths full hdlc controller with 64?byte buffers in both transmit and receive paths. configurable for sa bits or ds0 access rcl, rlos, rra, and rua1 alarms now interrupt on change of state 8.192 mhz clock synthesizer ability to monitor one ds0 channel in both the transmit and receive paths option to extend carrier loss criteria to a 1 ms period as per ets 300 233 automatic rai generation to ets 300 011 specifications ieee 1149.1 support functional description the receive side in each framer locates fas frame and crc and cas multiframe boundaries as well as detects incoming alarms including, carrier loss, loss of synchronization, ais and remote alarm. if needed, the receive side elastic store can be enabled in order to absorb the phase and frequency differences between the recovered e1 data stream and an asynchronous backplane clock which is provided at the rsysclk input. the clock applied at the rsysclk input can be either a 2.048 mhz clock or a 1.544 mhz clock. the rsysclk can be a burst clock with speeds up to 8.192 mhz. the transmit side in each framer is totally independent from the receive side in both the clock requirements and characteristics. data off of a backplane can be passed through a transmit side elastic store if necessary. the transmit formatter will provide the necessary frame/multiframe data overhead for e1 transmission. reader?s note: this data sheet assumes a particular nomenclature of the e1 operating environment. in each 125 us frame, there are 32 eight?bit timeslots numbered 0 to 31. timeslot 0 is transmitted first and received first. these 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. timeslot 0 is identical to channel 1, timeslot 1 is identical to channel 2, and so on. each timeslot (or channel) is made up of eight bits which are numbered 1 to 8. bit number 1 is the msb and is transmitted first. bit number 8 is the lsb and is transmitted last. throughout this data sheet, the following abbreviations will be used: fas frame alignment signal crc4 cyclical redundancy check cas channel associated signaling ccs common channel signaling mf multiframe sa additional bits si international bits e-bit crc4 error bits
ds21q44 3 of 105 ds21q44 enhanced quad e1 framer figure 1-1
ds21q44 4 of 105 table of contents 1. introduction .................................................................................................................. ............ 2 2. ds21q44 pin description ....................................................................................................... .. 7 3. ds21q44 pin function description ................................................................................ 13 4. ds21q44 register map........................................................................................................... .. 20 5. parallel port.................................................................................................................. ......... 24 6. control, id and test registers ..................................................................................... 24 7. status and information registers............................................................................. 34 8. error count registers....................................................................................................... 40 9. ds0 monitoring function................................................................................................... 43 10. signaling operation ........................................................................................................... .45 10.1 processor based signaling........................................................................................ 45 10.2 hardware based signaling........................................................................................ 48 11. per?channel code generation and loopback ................................................... 49 11.1 transmit side code generation............................................................................... 49 11.1.1 simple idle code insertion and per-channel loopback................................................... 49 11.1.2 per-channel code insertion .............................................................................................. 5 0 11.2 receive side code generation .................................................................................. 51 12. clock blocking registers ............................................................................................... 52 13. elastic stores operation ................................................................................................ 53 13.1 receive side............................................................................................................... .......... 54 13.2 transmit side .............................................................................................................. ....... 54 14. additional (sa) and international (si) bit operation .................................... 54 14.1 hardware scheme ........................................................................................................... 5 4 14.2 internal register scheme based on double-frame ..................................... 55 14.3 internal register scheme based on crc4 multiframe ............................... 57
ds21q44 5 of 105 15. hdlc controller for the sa bits or ds0 ................................................................. 59 15.1 general overview........................................................................................................... 59 15.2 hdlc status registers .................................................................................................. 60 15.3 basic operation details............................................................................................... 61 15.4 hdlc register description.......................................................................................... 62 16. interleaved pcm bus operation ................................................................................... 69 17. jtag-boundary scan architecture and test access port .......................... 72 17.1 description................................................................................................................ .......... 72 17.2 tap controller state machine................................................................................ 73 17.3 instruction register and instructions ............................................................. 75 17.4 test registers............................................................................................................. ....... 77 18. timing diagrams................................................................................................................ ...... 82 19. operating parameters ...................................................................................................... 92 20. 128-pin tqfp package specifications ........................................................................ 105
ds21q44 6 of 105 document revision history revision notes 12-22-98 initial release
ds21q44 7 of 105 2. ds21q44 pin description pin description sorted by pin number table 2-1 pin symbol type description 1 tchblk0 o transmit channel block from framer 0 2 tpos0 o transmit bipolar data from framer 0 3 tneg0 o transmit bipolar data from framer 0 4 rlink0 o receive link data from framer 0 5 rlclk0 o receive link clock from framer 0 6 rclk0 i receive clock for framer 0 7 rneg0 i receive bipolar data for framer 0 8 rpos0 i receive bipolar data for framer 0 9rsig0 [rchclk0] o [o] receive signaling output from framer 0 [receive channel clock from framer 0] 10 rchblk0 o receive channel block from framer 0 11 rsysclk0 i receive system clock for elastic store in framer 0 12 rsync0 i/o receive sync for framer 0 13 rser0 o receive serial data from framer 0 14 vss - signal ground 15 vdd - positive supply voltage 16 spare1 [rmsync0] - [o] reserved - must be left unconnected for normal operation [receive multiframe sync from framer 0] 17 rfsync0 o receive frame sync from framer 0 18 jtrst* [rlos/lotc0] i [o] jtag reset [receive loss of sync/loss of transmit clock from framer 0] 19 tclk0 i transmit clock for framer 0 20 tlclk0 o transmit link clock from framer 0 21 tsync0 i/o transmit sync for framer 0 22 tlink0 i transmit link data for framer 0 23 a0 i address bus bit 0; lsb 24 a1 i address bus bit 1 25 a2 i address bus bit 2 26 a3 i address bus bit 3 27 a4 i address bus bit 4 28 a5 i address bus bit 5 29 a6/ale (as) i address bus bit 6; msb or address latch enable (address strobe) 30 int* o receive alarm interrupt for all four framers 31 tsysclk1 i transmit system clock for elastic store in framer 1 32 tser1 i transmit serial data for framer 1 33 tssync1 i transmit sync for elastic store in framer 1 34 tsig1 [tchclk1] i [o] transmit signaling input for framer 1 [transmit channel clock from framer 1] 35 tchblk1 o transmit channel block from framer 1 36 tpos1 o transmit bipolar data from framer 1 37 tneg1 o transmit bipolar data from framer 1
ds21q44 8 of 105 pin symbol type description 38 rlink1 o receive link data from framer 1 39 rlclk1 o receive link clock from framer 1 40 rclk1 i receive clock for framer 1 41 rneg1 i receive bipolar data for framer 1 42 rpos1 i receive bipolar data for framer 1 43 rsig1 [rchclk1] o [o] receive signaling output from framer 1 [receive channel clock from framer 1] 44 rchblk1 o receive channel block from framer 1 45 rsysclk1 i receive system clock for elastic store in framer 1 46 a7 i address bus bit 7 47 fms i framer mode select 48 rsync1 i/o receive sync for framer 1 49 rser1 o receive serial data from framer 1 50 jtms [rmsync1] i [o] jtag test mode select [receive multiframe sync from framer 1] 51 rfsync1 o receive frame sync from framer 1 52 jtclk [rlos/lotc1] i [o] jtag test clock [receive loss of sync/loss of transmit clock from framer 1] 53 tclk1 i transmit clock for framer 1 54 tlclk1 o transmit link clock from framer 1 55 tsync1 i/o transmit sync for framer 1 56 tlink1 i transmit link data for framer 1 57 test i 3-state control for all output and i/o pins 58 fs0 i framer select 0 for parallel control port 59 fs1 i framer select 1 for parallel control port 60 cs* i chip select 61 bts i bus type select for parallel control port 62 rd*/(ds*) i read input (data strobe) 63 wr*/(r/w*) i write input (read/write) 64 mux i non-multiplexed or multiplexed bus select 65 tsysclk2 i transmit system clock for elastic store in framer 2 66 tser2 i transmit serial data for framer 2 67 tssync2 i transmit sync for elastic store in framer 2 68 tsig2 [tchclk2] i [o] transmit signaling input for framer 2 [transmit channel clock from framer 2] 69 tchblk2 o transmit channel block from framer 2 70 tpos2 o transmit bipolar data from framer 2 71 tneg2 o transmit bipolar data from framer 2 72 rlink2 o receive link data from framer 2 73 rlclk2 o receive link clock from framer 2 74 rclk2 i receive clock for framer 2 75 rneg2 i receive bipolar data for framer 2 76 rpos2 i receive bipolar data for framer 2 77 rsig2 [rchclk2] o [o] receive signaling output from framer 2 [receive channel clock from framer 2] 78 vss - signal ground
ds21q44 9 of 105 pin symbol type description 79 vdd - positive supply voltage 80 rchblk2 o receive channel block from framer 2 81 rsysclk2 i receive system clock for elastic store in framer 2 82 rsync2 i/o receive sync for framer 2 83 rser2 o receive serial data from framer 2 84 jtdi [rmsync2] i [o] jtag test data input [receive multiframe sync from framer 2] 85 rfsync2 o receive frame sync from framer 2 86 jtdo [rlos/lotc2] o [o] jtag test data output [receive loss of sync/loss of transmit clock from framer 2] 87 tclk2 i transmit clock for framer 2 88 tlclk2 o transmit link clock from framer 2 89 tsync2 i/o transmit sync for framer 2 90 tlink2 i transmit link data for framer 2 91 tsysclk3 i transmit system clock for elastic store in framer 3 92 tser3 i transmit serial data for framer 3 93 tssync3 i transmit sync for elastic store in framer 3 94 tsig3 [tchclk3] i transmit signaling input for framer 3 [transmit channel clock from framer 3] 95 tchblk3 o transmit channel block from framer 3 96 tpos3 o transmit bipolar data from framer 3 97 tneg3 o transmit bipolar data from framer 3 98 rlink3 o receive link data from framer 3 99 rlclk3 o receive link clock from framer 3 100 rclk3 i receive clock for framer 3 101 rneg3 i receive bipolar data for framer 3 102 rpos3 i receive bipolar data for framer 3 103 rsig3 [rchclk3] o [o] receive signaling output from framer 3 [receive channel clock from framer 3] 104 rchblk3 o receive channel block from framer 3 105 rsysclk3 i receive system clock for elastic store in framer 3 106 rsync3 i/o receive sync for framer 3 107 rser3 o receive serial data from framer 3 108 8mclk [rmsync3] o [o] 8 mhz clock [receive multiframe sync from framer 3] 109 rfsync3 o receive frame sync from framer 3 110 vss - signal ground 111 vdd - positive supply voltage 112 clksi [rlos/lotc3] i [o] 8mclk clock reference input [receive loss of sync/loss of transmit clock from framer 3] 113 tclk3 i transmit clock for framer 3 114 tlclk3 o transmit link clock from framer 3 115 tsync3 i/o transmit sync for framer 3 116 tlink3 i transmit link data for framer 3 117 d0 or ad0 i/o data bus bit or address/data bit 0; lsb 118 d1 or ad1 i/o data bus bit or address/data bit 1
ds21q44 10 of 105 pin symbol type description 119 d2 or ad2 i/o data bus bit or address/data bit 2 120 d3 or ad3 i/o data bus bit or address/data bit 3 121 d4 or ad4 i/o data bus bit or address/data bit 4 122 d5 or ad5 i/o data bus bit or address/data bit 5 123 d6 or ad6 i/o data bus bit or address/data bit 6 124 d7 or ad7 i/o data bus bit or address/data bit 7; msb 125 tsysclk0 i transmit system clock for elastic store in framer 0 126 tser0 i transmit serial data for framer 0 127 tssync0 i transmit sync for elastic store in framer 0 128 tsig0 [tchclk0] i [o] transmit signaling input for framer 0 [transmit channel clock from framer 0] note: 1. brackets [ ] indicate pin function when the ds21q44 is configured for emulation of the ds21q43, (fms = 1). pin description sorted by pin function, fms = 0 table 2-2 pin symbol type description 108 8mclk o 8 mhz clock 23 a0 i address bus bit 0; lsb 24 a1 i address bus bit 1 25 a2 i address bus bit 2 26 a3 i address bus bit 3 27 a4 i address bus bit 4 28 a5 i address bus bit 5 29 a6/ale (as) i address bus bit 6; msb or address latch enable (address strobe) 46 a7 i address bus bit 7 61 bts i bus type select for parallel control port 112 clksi i 8mclk clock reference input 60 cs* i chip select 117 d0 or ad0 i/o data bus bit or address/data bit 0; lsb 118 d1 or ad1 i/o data bus bit or address/data bit 1 119 d2 or ad2 i/o data bus bit or address/data bit 2 120 d3 or ad3 i/o data bus bit or address/data bit 3 121 d4 or ad4 i/o data bus bit or address/data bit 4 122 d5 or ad5 i/o data bus bit or address/data bit 5 123 d6 or ad6 i/o data bus bit or address/data bit 6 124 d7 or ad7 i/o data bus bit or address/data bit 7; msb 47 fms i framer mode select 58 fs0 i framer select 0 for parallel control port 59 fs1 i framer select 1 for parallel control port 30 int* o receive alarm interrupt for all four framers 52 jtclk i jtag test clock
ds21q44 11 of 105 pin symbol type description 84 jtdi i jtag test data input 86 jtdo o jtag test data output 50 jtms i jtag test mode select 18 jtrst* i jtag reset 64 mux i non-multiplexed or multiplexed bus select 10 rchblk0 o receive channel block from framer 0 44 rchblk1 o receive channel block from framer 1 80 rchblk2 o receive channel block from framer 2 104 rchblk3 o receive channel block from framer 3 6 rclk0 i receive clock for framer 0 40 rclk1 i receive clock for framer 1 74 rclk2 i receive clock for framer 2 100 rclk3 i receive clock for framer 3 62 rd*/(ds*) i read input (data strobe) 17 rfsync0 o receive frame sync from framer 0 51 rfsync1 o receive frame sync from framer 1 85 rfsync2 o receive frame sync from framer 2 109 rfsync3 o receive frame sync from framer 3 5 rlclk0 o receive link clock from framer 0 39 rlclk1 o receive link clock from framer 1 73 rlclk2 o receive link clock from framer 2 99 rlclk3 o receive link clock from framer 3 4 rlink0 o receive link data from framer 0 38 rlink1 o receive link data from framer 1 72 rlink2 o receive link data from framer 2 98 rlink3 o receive link data from framer 3 7 rneg0 i receive bipolar data for framer 0 41 rneg1 i receive bipolar data for framer 1 75 rneg2 i receive bipolar data for framer 2 101 rneg3 i receive bipolar data for framer 3 8 rpos0 i receive bipolar data for framer 0 42 rpos1 i receive bipolar data for framer 1 76 rpos2 i receive bipolar data for framer 2 102 rpos3 i receive bipolar data for framer 3 13 rser0 o receive serial data from framer 0 49 rser1 o receive serial data from framer 1 83 rser2 o receive serial data from framer 2 107 rser3 o receive serial data from framer 3 9 rsig0 o receive signaling output from framer 0 43 rsig1 o receive signaling output from framer 1 77 rsig2 o receive signaling output from framer 2 103 rsig3 o receive signaling output from framer 3 12 rsync0 i/o receive sync for framer 0 48 rsync1 i/o receive sync for framer 1 82 rsync2 i/o receive sync for framer 2
ds21q44 12 of 105 pin symbol type description 106 rsync3 i/o receive sync for framer 3 11 rsysclk0 i receive system clock for elastic store in framer 0 45 rsysclk1 i receive system clock for elastic store in framer 1 81 rsysclk2 i receive system clock for elastic store in framer 2 105 rsysclk3 i receive system clock for elastic store in framer 3 16 spare1 - reserved - must be left unconnected for normal operation 1 tchblk0 o transmit channel block from framer 0 35 tchblk1 o transmit channel block from framer 1 69 tchblk2 o transmit channel block from framer 2 95 tchblk3 o transmit channel block from framer 3 19 tclk0 i transmit clock for framer 0 53 tclk1 i transmit clock for framer 1 87 tclk2 i transmit clock for framer 2 113 tclk3 i transmit clock for framer 3 57 test i 3-state control for all output and i/o pins 20 tlclk0 o transmit link clock from framer 0 54 tlclk1 o transmit link clock from framer 1 88 tlclk2 o transmit link clock from framer 2 114 tlclk3 o transmit link clock from framer 3 22 tlink0 i transmit link data for framer 0 56 tlink1 i transmit link data for framer 1 90 tlink2 i transmit link data for framer 2 116 tlink3 i transmit link data for framer 3 3 tneg0 o transmit bipolar data from framer 0 37 tneg1 o transmit bipolar data from framer 1 71 tneg2 o transmit bipolar data from framer 2 97 tneg3 o transmit bipolar data from framer 3 2 tpos0 o transmit bipolar data from framer 0 36 tpos1 o transmit bipolar data from framer 1 70 tpos2 o transmit bipolar data from framer 2 96 tpos3 o transmit bipolar data from framer 3 126 tser0 i transmit serial data for framer 0 32 tser1 i transmit serial data for framer 1 66 tser2 i transmit serial data for framer 2 92 tser3 i transmit serial data for framer 3 128 tsig0 i transmit signaling input for framer 0 34 tsig1 i transmit signaling input for framer 1 68 tsig2 i transmit signaling input for framer 2 94 tsig3 i transmit signaling input for framer 3 127 tssync0 i transmit sync for elastic store in framer 0 33 tssync1 i transmit sync for elastic store in framer 1 67 tssync2 i transmit sync for elastic store in framer 2 93 tssync3 i transmit sync for elastic store in framer 3 21 tsync0 i/o transmit sync for framer 0 55 tsync1 i/o transmit sync for framer 1
ds21q44 13 of 105 pin symbol type description 89 tsync2 i/o transmit sync for framer 2 115 tsync3 i/o transmit sync for framer 3 125 tsysclk0 i transmit system clock for elastic store in framer 0 31 tsysclk1 i transmit system clock for elastic store in framer 1 65 tsysclk2 i transmit system clock for elastic store in framer 2 91 tsysclk3 i transmit system clock for elastic store in framer 3 15 vdd - positive supply voltage 79 vdd - positive supply voltage 111 vdd - positive supply voltage 14 vss - signal ground 78 vss - signal ground 110 vss - signal ground 63 wr*/(r/w*) i write input (read/write) 3. ds21q44 pin function description transmit side pins signal name: tclk signal description: transmit clock signal type: input a 2.048 mhz primary clock. used to clock data through the transmit side formatter. signal name: tser signal description: transmit serial data signal type: input transmit nrz serial data. sampled on the falling edge of tclk when the transmit side elastic store is disabled. sampled on the falling edge of tsysclk when the transmit side elastic store is enabled. signal name: tchclk signal description: transmit channel clock signal type: output a 256 khz clock which pulses high during the lsb of each channel. synchronous with tclk when the transmit side elastic store is disabled. synchronous with tsysclk when the transmit side elastic store is enabled. useful for parallel to serial conversion of channel data. this function is available when fms = 1 (ds21q43 emulation). signal name: tchblk signal description: transmit channel block signal type: output a user programmable output that can be forced high or low during any of the 32 e1 channels. synchronous with tclk when the transmit side elastic store is disabled. synchronous with tsysclk when the transmit side elastic store is enabled. useful for blocking clocks to a serial uart or lapd controller in applications where not all e1 channels are used such as fractional e1, 384 kbps (h0), 768 kbps, 1920 bps (h12) or isdn?pri . also useful for locating individual channels in drop?and?insert applications, for external per?channel loopback, and for per?channel conditioning. see section 12 for details.
ds21q44 14 of 105 signal name: tsysclk signal description: transmit system clock signal type: input 1.544 mhz or 2.048 mhz clock. only used when the transmit side elastic store function is enabled. should be tied low in applications that do not use the transmit side elastic store. can be burst at rates up to 8.192 mhz. signal name: tlclk signal description: transmit link clock signal type: output 4 khz to 20 khz demand clock for the tlink input. see section 14 for details. signal name: tlink signal description: transmit link data signal type: input if enabled, this pin will be sampled on the falling edge of tclk for data insertion into any combination of the sa bit positions (sa4 to sa8). see section 14 for details. signal name: tsync signal description: transmit sync signal type: input /output a pulse at this pin will establish either frame or multiframe boundaries for the transmit side. this pin can also be programmed to output either a frame or multiframe pulse. always synchronous with tclk. signal name: tssync signal description: transmit system sync signal type: input only used when the transmit side elastic store is enabled. a pulse at this pin will establish either frame or multiframe boundaries for the transmit side. should be tied low in applications that do not use the transmit side elastic store. always synchronous with tsysclk. signal name: tsig signal description: transmit signaling input signal type: input when enabled, this input will sample signaling bits for insertion into outgoing pcm e1 data stream. sampled on the falling edge of tclk when the transmit side elastic store is disabled. sampled on the falling edge of tsysclk when the transmit side elastic store is enabled. this function is available when fms = 0. signal name: tpos signal description: transmit positive data output signal type: output updated on the rising edge of tclk with the bipolar data out of the transmit side formatter. can be programmed to source nrz data via the output data format (tcr1.7) control bit. signal name: tneg signal description: transmit negative data output signal type: output updated on the rising edge of tclk with the bipolar data out of the transmit side formatter.
ds21q44 15 of 105 receive side pins signal name: rlink signal description: receive link data signal type: output updated with full recovered e1 data stream on the rising edge of rclk. signal name: rlclk signal description: receive link clock signal type: output a 4 khz to 20 khz clock for the rlink output. used for sampling sa bits. signal name: rclk signal description: receive clock input signal type: input 2.048 mhz clock that is used to clock data through the receive side framer. signal name: rchclk signal description: receive channel clock signal type: output a 256 khz clock which pulses high during the lsb of each channel. synchronous with rclk when the receive side elastic store is disabled. synchronous with rsysclk when the receive side elastic store is enabled. useful for parallel to serial conversion of channel data. this function is available when fms = 1 (ds21q43 emulation). signal name: rchblk signal description: receive channel block signal type: output a user programmable output that can be forced high or low during any of the 32 e1 channels. synchronous with rclk when the receive side elastic store is disabled. synchronous with rsysclk when the receive side elastic store is enabled. useful for blocking clocks to a serial uart or lapd controller in applications where not all e1 channels are used such as fractional e1, 384k bps service, 768k bps, or isdn?pri. also useful for locating individual channels in drop?and?insert applications, for external per?channel loopback, and for per?channel conditioning. see section 12 for details. signal name: rser signal description: receive serial data signal type: output received nrz serial data. updated on rising edges of rclk when the receive side elastic store is disabled. updated on the rising edges of rsysclk when the receive side elastic store is enabled. signal name: rsync signal description: receive sync signal type: input /output an extracted pulse, one rclk wide, is output at this pin which identifies either frame or cas/crc multiframe boundaries. if the receive side elastic store is enabled, then this pin can be enabled to be an input at which a frame or multiframe boundary pulse synchronous with rsysclk is applied.
ds21q44 16 of 105 signal name: rfsync signal description: receive frame sync signal type: output an extracted 8 khz pulse, one rclk wide, is output at this pin which identifies frame boundaries. signal name: rmsync signal description: receive multiframe sync signal type: output an extracted pulse, one rsysclk wide, is output at this pin which identifies multiframe boundaries. if the receive side elastic store is disabled, then this output will output multiframe boundaries associated with rclk. this function is available when fms = 1 (ds21q43 emulation). signal name: rsysclk signal description: receive system clock signal type: input 1.544 mhz or 2.048 mhz clock. only used when the elastic store function is enabled. should be tied low in applications that do not use the elastic store. can be burst at rates up to 8.192 mhz. signal name: rsig signal description: receive signaling output signal type: output outputs signaling bits in a pcm format. updated on rising edges of rclk when the receive side elastic store is disabled. updated on the rising edges of rsysclk when the receive side elastic store is enabled. this function is available when fms = 0. signal name: rlos/lotc signal description: receive loss of sync / loss of transmit clock signal type: output a dual function output that is controlled by the tcr2.0 control bit. this pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the tclk pin has not been toggled for 5 usec. this function is available when fms = 1 (ds21q43 emulation). signal name: clksi signal description: 8 mhz clock reference signal type: input a 2.048 mhz reference clock used in the generation of 8mclk. this function is available when fms = 0. signal name: 8mclk signal description: 8 mhz clock signal type: output a 8.192 mhz output clock that is referenced to the clock that is input at the clksi pin. this function is available when fms = 0.
ds21q44 17 of 105 signal name: rpos signal description: receive positive data input signal type: input sampled on the falling edge of rclk for data to be clocked through the receive side framer. rpos and rneg can be tied together for an nrz interface. connecting rpos to rneg disables the bipolar violation monitoring circuitry. signal name: rneg signal description: receive negative data input signal type: input sampled on the falling edge of rclk for data to be clocked through the receive side framer. rpos and rneg can be tied together for an nrz interface. connecting rpos to rneg disables the bipolar violation monitoring circuitry. parallel control port pins signal name: int* signal description: interrupt signal type: output flags host controller during conditions and change of conditions defined in the status registers 1 and 2 and the fdl status register. active low, open drain output. signal name: fms signal description: framer mode select signal type: input set low to select ds21q44 feature set. set high to select ds21q43 emulation. signal name: mux signal description: bus operation signal type: input set low to select non?multiplexed bus operation. set high to select multiplexed bus operation. signal name: d0 to d7 / ad0 to ad7 signal description: data bus or address/data bus signal type: input /output in non?multiplexed bus operation (mux = 0), serves as the data bus. in multiplexed bus operation (mux = 1), serves as a 8?bit multiplexed address / data bus. signal name: a0 to a5, a7 signal description: address bus signal type: input in non?multiplexed bus operation (mux = 0), serves as the address bus. in multiplexed bus operation (mux = 1), these pins are not used and should be tied low. signal name: ale (as) / a6 signal description: address latch enable (address strobe) or a6 signal type: input in non?multiplexed bus operation (mux = 0), serves as address bit 6. in multiplexed bus operation (mux = 1), serves to demultiplex the bus on a positive?going edge.
ds21q44 18 of 105 signal name: bts signal description: bus type select signal type: input strap high to select motorola bus timing; strap low to select intel bus timing. this pin controls the function of the rd*(ds*), ale(as), and wr*(r/w*) pins. if bts = 1, then these pins assume the function listed in parenthesis (). signal name: rd* (ds*) signal description: read input (data strobe) signal type: input rd* and ds* are active low signals. note: ds is active high when mux=1. refer to bus timing diagrams in section 19 . signal name: fs0 and fs1 signal description: framer selects signal type: input selects which of the four framers to be accessed. signal name: cs* signal description: chip select signal type: input must be low to read or write to the device. cs* is an active low signal. signal name: wr* (r/w*) signal description: write input (read/write) signal type: input wr* is an active low signal. test access port pins signal name: test signal description: 3?state control signal type: input set high to 3?state all output and i/o pins (including the parallel control port). set low for normal operation. useful in board level testing. signal name: jtrst* signal description: ieee 1149.1 test reset signal type: input this signal is used to asynchronously reset the test access port controller. at power up, jtrst* must be set low and then high. this action will set the device into the boundary scan bypass mode allowing normal device operation. if boundary scan is not used, this pin should be held low. this function is available when fms = 0. signal name: jtms signal description: ieee 1149.1 test mode select signal type: input this pin is sampled on the rising edge of jtclk and is used to place the test port into the various defined ieee 1149.1 states. if not used, this pin should be pulled high. this function is available when fms = 0.
ds21q44 19 of 105 signal name: jtclk signal description: ieee 1149.1 test clock signal signal type: input this signal is used to shift data into jtdi on the rising edge and out of jtdo on the falling edge. if not used, this pin should be tied to vss. this function is available when fms = 0. signal name: jtdi signal description: ieee 1149.1 test data input signal type: input test instructions and data are clocked into this pin on the rising edge of jtclk. if not used, this pin should be pulled high. this function is available when fms = 0. signal name: jtdo signal description: ieee 1149.1 test data output signal type: output test instructions and data are clocked out of this pin on the falling edge of jtclk. if not used, this pin should be left unconnected. this function is available when fms = 0. supply pins signal name: vdd signal description: positive supply signal type: supply 2.97 to 3.63 volts. signal name: vss signal description: signal ground signal type: supply 0.0 volts.
ds21q44 20 of 105 4. ds21q44 register map register map sorted by address table 4-1 address r/w register name register abbreviation 00 r bpv or code violation count 1 vcr1 01 r bpv or code violation count 2 vcr2 02 r crc4 error count 1 / fas error count 1 crccr1 03 r crc4 error count 2 crccr2 04 r e-bit count 1 / fas error count 2 ebcr1 05 r e-bit count 2 ebcr2 06 r/w status 1 sr1 07 r/w status 2 sr2 08 r/w receive information rir 09 r/w test 2 test2 (set to 00h) 0a ? not used (set to 00h) 0b ? not used (set to 00h) 0c ? not used (set to 00h) 0d ? not used (set to 00h) 0e ? not used (set to 00h) 0f r device id idr 10 r/w receive control 1 rcr1 11 r/w receive control 2 rcr2 12 r/w transmit control 1 tcr1 13 r/w transmit control 2 tcr2 14 r/w common control 1 ccr1 15 r/w test 1 test1 (set to 00h) 16 r/w interrupt mask 1 imr1 17 r/w interrupt mask 2 imr2 18 ? not used (set to 00h) 19 ? not used (set to 00h) 1a r/w common control 2 ccr2 1b r/w common control 3 ccr3 1c r/w transmit sa bit control tsacr 1d r/w common control 6 ccr6 1e r synchronizer status ssr 1f r receive non-align frame rnaf 20 r/w transmit align frame taf 21 r/w transmit non-align frame tnaf 22 r/w transmit channel blocking 1 tcbr1 23 r/w transmit channel blocking 2 tcbr2 24 r/w transmit channel blocking 3 tcbr3 25 r/w transmit channel blocking 4 tcbr4 26 r/w transmit idle 1 tir1 27 r/w transmit idle 2 tir2
ds21q44 21 of 105 address r/w register name register abbreviation 28 r/w transmit idle 3 tir3 29 r/w transmit idle 4 tir4 2a r/w transmit idle definition tidr 2b r/w receive channel blocking 1 rcbr1 2c r/w receive channel blocking 2 rcbr2 2d r/w receive channel blocking 3 rcbr3 2e r/w receive channel blocking 4 rcbr4 2f r receive align frame raf 30 r receive signaling 1 rs1 31 r receive signaling 2 rs2 32 r receive signaling 3 rs3 33 r receive signaling 4 rs4 34 r receive signaling 5 rs5 35 r receive signaling 6 rs6 36 r receive signaling 7 rs7 37 r receive signaling 8 rs8 38 r receive signaling 9 rs9 39 r receive signaling 10 rs10 3a r receive signaling 11 rs11 3b r receive signaling 12 rs12 3c r receive signaling 13 rs13 3d r receive signaling 14 rs14 3e r receive signaling 15 rs15 3f r receive signaling 16 rs16 40 r/w transmit signaling 1 ts1 41 r/w transmit signaling 2 ts2 42 r/w transmit signaling 3 ts3 43 r/w transmit signaling 4 ts4 44 r/w transmit signaling 5 ts5 45 r/w transmit signaling 6 ts6 46 r/w transmit signaling 7 ts7 47 r/w transmit signaling 8 ts8 48 r/w transmit signaling 9 ts9 49 r/w transmit signaling 10 ts10 4a r/w transmit signaling 11 ts11 4b r/w transmit signaling 12 ts12 4c r/w transmit signaling 13 ts13 4d r/w transmit signaling 14 ts14 4e r/w transmit signaling 15 ts15 4f r/w transmit signaling 16 ts16 50 r/w transmit si bits align frame tsiaf 51 r/w transmit si bits non-align frame tsinaf 52 r/w transmit remote alarm bits tra 53 r/w transmit sa4 bits tsa4
ds21q44 22 of 105 address r/w register name register abbreviation 54 r/w transmit sa5 bits tsa5 55 r/w transmit sa6 bits tsa6 56 r/w transmit sa7 bits tsa7 57 r/w transmit sa8 bits tsa8 58 r receive si bits align frame rsiaf 59 r receive si bits non-align frame rsinaf 5a r receive remote alarm bits rra 5b r receive sa4 bits rsa4 5c r receive sa5 bits rsa5 5d r receive sa6 bits rsa6 5e r receive sa7 bits rsa7 5f r receive sa8 bits rsa8 60 r/w transmit channel 1 tc1 61 r/w transmit channel 2 tc2 62 r/w transmit channel 3 tc3 63 r/w transmit channel 4 tc4 64 r/w transmit channel 5 tc5 65 r/w transmit channel 6 tc6 66 r/w transmit channel 7 tc7 67 r/w transmit channel 8 tc8 68 r/w transmit channel 9 tc9 69 r/w transmit channel 10 tc10 6a r/w transmit channel 11 tc11 6b r/w transmit channel 12 tc12 6c r/w transmit channel 13 tc13 6d r/w transmit channel 14 tc14 6e r/w transmit channel 15 tc15 6f r/w transmit channel 16 tc16 70 r/w transmit channel 17 tc17 71 r/w transmit channel 18 tc18 72 r/w transmit channel 19 tc19 73 r/w transmit channel 20 tc20 74 r/w transmit channel 21 tc21 75 r/w transmit channel 22 tc22 76 r/w transmit channel 23 tc23 77 r/w transmit channel 24 tc24 78 r/w transmit channel 25 tc25 79 r/w transmit channel 26 tc26 7a r/w transmit channel 27 tc27 7b r/w transmit channel 28 tc28 7c r/w transmit channel 29 tc29 7d r/w transmit channel 30 tc30 7e r/w transmit channel 31 tc31 7f r/w transmit channel 32 tc32
ds21q44 23 of 105 address r/w register name register abbreviation 80 r/w receive channel 1 rc1 81 r/w receive channel 2 rc2 82 r/w receive channel 3 rc3 83 r/w receive channel 4 rc4 84 r/w receive channel 5 rc5 85 r/w receive channel 6 rc6 86 r/w receive channel 7 rc7 87 r/w receive channel 8 rc8 88 r/w receive channel 9 rc9 89 r/w receive channel 10 rc10 8a r/w receive channel 11 rc11 8b r/w receive channel 12 rc12 8c r/w receive channel 13 rc13 8d r/w receive channel 14 rc14 8e r/w receive channel 15 rc15 8f r/w receive channel 16 rc16 90 r/w receive channel 17 rc17 91 r/w receive channel 18 rc18 92 r/w receive channel 19 rc19 93 r/w receive channel 20 rc20 94 r/w receive channel 21 rc21 95 r/w receive channel 22 rc22 96 r/w receive channel 23 rc23 97 r/w receive channel 24 rc24 98 r/w receive channel 25 rc25 99 r/w receive channel 26 rc26 9a r/w receive channel 27 rc27 9b r/w receive channel 28 rc28 9c r/w receive channel 29 rc29 9d r/w receive channel 30 rc30 9e r/w receive channel 31 rc31 9f r/w receive channel 32 rc32 a0 r/w transmit channel control 1 tcc1 a1 r/w transmit channel control 2 tcc2 a2 r/w transmit channel control 3 tcc3 a3 r/w transmit channel control 4 tcc4 a4 r/w receive channel control 1 rcc1 a5 r/w receive channel control 2 rcc2 a6 r/w receive channel control 3 rcc3 a7 r/w receive channel control 4 rcc4 a8 r/w common control 4 ccr4 a9 r transmit ds0 monitor tds0m aa r/w common control 5 ccr5 ab r receive ds0 monitor rds0m
ds21q44 24 of 105 address r/w register name register abbreviation ac r/w test 3 test3 (set to 00h) ad ? not used (set to 00h) ae ? not used (set to 00h) af ? not used (set to 00h) b0 r/w hdlc control register hcr b1 r/w hdlc status register hsr b2 r/w hdlc interrupt mask register himr b3 r/w receive hdlc information register rhir b4 r/w receive hdlc fifo register rhfr b5 r/w interleave bus operation register ibo b6 r/w transmit hdlc information register thir b7 r/w transmit hdlc fifo register thfr b8 r/w receive hdlc ds0 control register 1 rdc1 b9 r/w receive hdlc ds0 control register 2 rdc2 ba r/w transmit hdlc ds0 control register 1 tdc1 bb r/w transmit hdlc ds0 control register 2 tdc2 bc ? not used (set to 00h) bd ? not used (set to 00h) be ? not used (set to 00h) bf ? not used (set to 00h) notes: 1. test registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all zeros) on power? up initialization to insure proper operation. 2. register banks cxh, dxh, exh, and fxh are not accessible. 5. parallel port the ds21q44 is controlled via either a non?multiplexed (mux = 0) or a multiplexed (mux = 1) bus by an external microcontroller or microprocessor. the ds21q44 can operate with either intel or motorola bus timing configurations. if the bts pin is tied low, intel timing will be selected; if tied high, motorola timing will be selected. all motorola bus signals are listed in parenthesis (). see the timing diagrams in the a.c. electrical characteristics in section 19 for more details. 6. control, id and test registers the operation of each framer within the ds21q44 is configured via a set of ten control registers. typically, the control registers are only accessed when the system is first powered up. once a channel in the ds21q44 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. there are two receive control register (rcr1 and rcr2), two transmit control registers (tcr1 and tcr2), and six common control registers (ccr1 to ccr6). each of the ten registers are described in this section. there is a device identification register (idr) at address 0fh. the msb of this read?only register is fixed to a one indicating that the ds21q44 is present. the t1 pin?for?pin compatible version of the ds21q44 is the ds21q42 and it also has an id register at address 0fh and the user can read the msb to determine which chip is present since in the ds21q42 the msb will be set to a zero and in the ds21q44 it will be set to a one. the lower four bits of the idr are used to display the die revision of the chip.
ds21q44 25 of 105 power?up sequence the ds21q44 does not automatically clear its register space on power?up. after the supplies are stable, each of the four framer?s register space should be configured for operation by writing to all of the internal registers. this includes setting the test and all unused registers to 00hex. this can be accomplished using a two-pass approach on each framer within the ds21q44. 1. clear framer?s register space by writing 00h to the addresses 00h through 0bfh. 2. program required registers to achieve desired operating mode. note: when emulating the ds21q43 feature set (fms = 1), the full address space (00h through 0bfh) must be initialized. ds21q43 emulation require address pin a7 to be used. finally, after the tsysclk and rsysclk inputs are stable, the esr bit should be toggled from a zero to a one (this step can be skipped if the elastic stores are disabled). idr: device identification register (address=0f hex) (msb) (lsb) t1e1 0 0 0 id3 id2 id1 id0 symbol position name and description t1e1 idr.7 t1 or e1 chip determination bit. 0=t1 chip 1=e1 chip id3 idr.3 chip revision bit 3. msb of a decimal code that represents the chip revision. id2 idr.1 chip revision bit 2. id1 idr.2 chip revision bit 1. id0 idr.0 chip revision bit 0. lsb of a decimal code that represents the chip revision. rcr1: receive control register 1 (address=10 hex) (msb) (lsb) rsmf rsm rsio ? ? frc synce resync symbol position name and description rsmf rcr1.7 rsync multiframe function. only used if the rsync pin is programmed in the multiframe mode (rcr1.6=1). 0 = rsync outputs cas multiframe boundaries 1 = rsync outputs crc4 multiframe boundaries rsm rcr1.6 rsync mode select. 0 = frame mode (see the timing in section 18) 1 = multiframe mode (see the timing in section 18)
ds21q44 26 of 105 symbol position name and description rsio rcr1.5 rsync i/o select. (note: this bit must be set to zero when rcr2.1=0). 0 = rsync is an output (depends on rcr1.6) 1 = rsync is an input (only valid if elastic store enabled) ? rcr1.4 not assigned. should be set to zero when written. ? rcr1.3 not assigned. should be set to zero when written. frc rcr1.2 frame resync criteria. 0 = resync if fas received in error 3 consecutive times 1 = resync if fas or bit 2 of non?fas is received in error 3 consecutive times synce rcr1.1 sync enable. 0 = auto resync enabled 1 = auto resync disabled resync rcr1.0 resync. when toggled from low to high, a resync is initiated. must be cleared and set again for a subsequent resync. sync/resync criteria table 6?1 frame or multiframe level sync criteria resync criteria itu spec. fas fas present in frame n and n + 2, and fas not present in frame n + 1 three consecutive incorrect fas received alternate (rcr1.2=1) the above criteria is met or three consecutive incorrect bit 2 of non?fas received g.706 4.1.1 4.1.2 crc4 two valid mf alignment words found within 8 ms 915 or more crc4 code words out of 1000 received in error g.706 4.2 and 4.3.2 cas valid mf alignment word found and previous timeslot 16 contains code other than all zeros two consecutive mf alignment words received in error g.732 5.2
ds21q44 27 of 105 rcr2: receive control register 2 (address=11 hex) (msb) (lsb) sa8s sa7s sa6s sa5s sa4s rbcs rese ? symbol position name and description sa8s rcr2.7 sa8 bit select. set to one to have rlclk pulse at the sa8 bit position; set to zero to force rlclk low during sa8 bit position. see section 18 for timing details. sa7s rcr2.6 sa7 bit select. set to one to have rlclk pulse at the sa7 bit position; set to zero to force rlclk low during sa7 bit position. see section 18 for timing details. sa6s rcr2.5 sa6 bit select. set to one to have rlclk pulse at the sa6 bit position; set to zero to force rlclk low during sa6 bit position. see section 18 for timing details. sa5s rcr2.4 sa5 bit select. set to one to have rlclk pulse at the sa5 bit position; set to zero to force rlclk low during sa5 bit position. see section 18 for timing details. sa4s rcr2.3 sa4 bit select. set to one to have rlclk pulse at the sa4 bit position; set to zero to force rlclk low during sa4 bit position. see section 18 for timing details. rbcs rcr2.2 receive side backplane clock select. 0 = if rsysclk is 1.544 mhz 1 = if rsysclk is 2.048 mhz rese rcr2.1 receive side elastic store enable. 0 = elastic store is bypassed 1 = elastic store is enabled ? rcr2.0 not assigned. should be set to zero when written. tcr1: transmit control register 1 (address=12 hex) (msb) (lsb) odf tfpt t16s tua1 tsis tsa1 tsm tsio symbol position name and description odf tcr1.7 output data format. 0 = bipolar data at tpos and tneg 1 = nrz data at tpos; tneg=0 tfpt tcr1.6 transmit timeslot 0 pass through. 0 = fas bits/sa bits/remote alarm sourced internally from the taf and tnaf registers 1 = fas bits/sa bits/remote alarm sourced from tser t16s tcr1.5 transmit timeslot 16 data select. 0 = sample timeslot 16 at tser pin 1 = source timeslot 16 from ts0 to ts15 registers
ds21q44 28 of 105 symbol position name and description tua1 tcr1.4 transmit unframed all ones. 0 = transmit data normally 1 = transmit an unframed all one?s code at tpos and tneg tsis tcr1.3 transmit international bit select. 0 = sample si bits at tser pin 1 = source si bits from taf and tnaf registers (in this mode, tcr1.6 must be set to 0) tsa1 tcr1.2 transmit signaling all ones. 0 = normal operation 1 = force timeslot 16 in every frame to all ones tsm cr1.1 tsync mode select. 0 = frame mode (see the timing in section 18) 1 = cas and crc4 multiframe mode (see the timing in section 18) tsio tcr1.0 tsync i/o select. 0 = tsync is an input 1 = tsync is an output notes: see figure 18?15 for more details about how the transmit control registers affect the operation of the ds21q44. tcr2: transmit control register 2 (address=13 hex) (msb) (lsb) sa8s sa7s sa6s sa5s sa4s odm aebe pf symbol position name and description sa8s tcr2.7 sa8 bit select. set to one to source the sa8 bit from the tlink pin; set to zero to not source the sa8 bit. see section 18 for timing details. sa7s tcr2.6 sa7 bit select. set to one to source the sa7 bit from the tlink pin; set to zero to not source the sa7 bit. see section 18 for timing details. sa6s tcr2.5 sa6 bit select. set to one to source the sa6 bit from the tlink pin; set to zero to not source the sa6 bit. see section 18 for timing details. sa5s tcr2.4 sa5 bit select. set to one to source the sa5 bit from the tlink pin; set to zero to not source the sa5 bit. see section 18 for timing details. sa4s tcr2.3 sa4 bit select. set to one to source the sa4 bit from the tlink pin; set to zero to not source the sa4 bit. see section 18 for timing details.
ds21q44 29 of 105 symbol position name and description odm tcr2.2 output data mode. 0 = pulses at tposo and tnego are one full tclko period wide 1 = pulses at tposo and tnego are 1/2 tclko period wide aebe tcr2.1 automatic e?bit enable. 0 = e?bits not automatically set in the transmit direction 1 = e?bits automatically set in the transmit direction pf tcr2.0 function of rlos/lotc pin. 0 = receive loss of sync (rlos) 1 = loss of transmit clock (lotc) ccr1: common control register 1 (address=14 hex) (msb) (lsb) flb thdb3 tg802 tcrc4 rsm rhdb3 rg802 rcrc4 symbol position name and description flb ccr1.7 framer loopback. 0=loopback disabled 1=loopback enabled thdb3 ccr1.6 transmit hdb3 enable. 0=hdb3 disabled 1=hdb3 enabled tg802 ccr1.5 transmit g.802 enable. see section 18 for details. 0=do not force tchblk high during bit 1 of timeslot 26 1=force tchblk high during bit 1 of timeslot 26 tcrc4 ccr1.4 transmit crc4 enable. 0=crc4 disabled 1=crc4 enabled rsm ccr1.3 receive signaling mode select. 0=cas signaling mode 1=ccs signaling mode rhdb3 ccr1.2 receive hdb3 enable. 0=hdb3 disabled 1=hdb3 enabled rg802 ccr1.1 receive g.802 enable. see section 18 for details. 0=do not force rchblk high during bit 1 of timeslot 26 1=force rchblk high during bit 1 of timeslot 26 rcrc4 ccr1.0 receive crc4 enable. 0=crc4 disabled 1=crc4 enabled
ds21q44 30 of 105 framer loopback when ccr1.7 is set to a one, the framer will enter a framer loopback (flb) mode. see figure 1?1 for more details. this loopback is useful in testing and debugging applications. in flb, the framer will loop data from the transmit side back to the receive side. when flb is enabled, the following will occur: 1. data will be transmitted as normal at tpos and tneg. 2. data input via rpos and rneg will be ignored. 3. the rclk output will be replaced with the tclk input. ccr2: common control register 2 (address=1a hex) (msb) (lsb) ecus vcrfs aais ara rserc lotcmc rff rfe symbol position name and description ecus ccr2.7 error counter update select. see section 8 for details. 0=update error counters once a second 1=update error counters every 62.5 ms (500 frames) vcrfs ccr2.6 vcr function select. see section 8 for details. 0=count bipolar violations (bpvs) 1=count code violations (cvs) aais ccr2.5 automatic ais generation. 0=disabled 1=enabled ara ccr2.4 automatic remote alarm generation. 0=disabled 1=enabled rserc ccr2.3 rser control. 0=allow rser to output data as received under all conditions 1=force rser to one under loss of frame alignment conditions lotcmc ccr2.2 loss of transmit clock mux control. determines whether the transmit side formatter should switch to the ever present rclk if the tclk should fail to transition (see figure 1?1). 0=do not switch to rclk if tclk stops 1=switch to rclk if tclk stops rff ccr2.1 receive force freeze. freezes receive side signaling at rsig (and rser if ccr3.3=1); will override receive freeze enable (rfe). see section 10 or details. 0=do not force a freeze event 1=force a freeze event rfe ccr2.0 receive freeze enable. see section 10 for details. 0=no freezing of receive signaling data will occur 1=allow freezing of receive signaling data at rsig (and rser if ccr3.3=1).
ds21q44 31 of 105 automatic alarm generation the ds21q44 can be programmed to automatically transmit ais or remote alarm. when automatic ais generation is enabled (ccr2.5 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, ais alarm (all one?s) reception, or loss of receive carrier (or signal). if any one (or more) of the above conditions is present, then the framer will transmit an ais alarm. when automatic rai generation is enabled (ccr2.4 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, ais alarm (all one?s) reception, loss of receive carrier or if crc4 multiframe synchronization (if enabled) cannot be found within 128 ms of fas synchronization. if any one (or more) of the above conditions is present, then the framer will transmit a rai alarm. rai generation conforms to ets 300 011 specifications and a constant remote alarm will be transmitted if the framer cannot find crc4 multiframe synchronization within 400 ms as per g.706. it is an illegal state to have both ccr2.4 and ccr2.5 set to one at the same time. ccr3: common control register 3 (address=1b hex) (msb) (lsb) tese tcbfs tirfs ? rsre thse tbcs rcla symbol position name and description tese ccr3.7 transmit side elastic store enable. 0=elastic store is bypassed 1=elastic store is enabled tcbfs ccr3.6 transmit channel blocking registers (tcbr) function select. 0=tcbrs define the operation of the tchblk output pin 1=tcbrs define which signaling bits are to be inserted tirfs ccr3.5 transmit idle registers (tir) function select. see section 11 for details. 0=tirs define in which channels to insert idle code 1=tirs define in which channels to insert data from rser (i.e., per channel loopback function) ? ccr3.4 not assigned. should be set to zero when written. rsre ccr3.3 receive side signaling re?insertion enable. see section 10 for details. 0=do not re?insert signaling bits into the data stream presented at the rser pin 1=re?insert the signaling bits into data stream presented at the rser pin thse ccr3.2 transmit side hardware signaling insertion enable. see section 10 for details. 0=do not insert signaling from the tsig pin into the data stream presented at the tser pin 1=insert signaling from the tsig pin into the data stream
ds21q44 32 of 105 symbol position name and description presented at the tser pin tbcs ccr3.1 transmit side backplane clock select. 0=if tsysclk is 1.544 mhz 1=if tsysclk is 2.048 mhz rcla ccr3.0 receive carrier loss (rcl) alternate criteria. 0=rcl declared upon 255 consecutive zeros (125 us) 1=rcl declared upon 2048 consecutive zeros (1 ms) ccr4: common control register 4 (address=a8 hex) (msb) (lsb) rlb ? ? tcm4 tcm3 tcm2 tcm1 tcm0 symbol position name and description rlb ccr4.7 remote loopback. 0 = loopback disabled 1 = loopback enabled ? ccr4.6 not assigned. should be set to zero when written. ? ccr4.5 not assigned. should be set to zero when written. tcm4 ccr4.4 transmit channel monitor bit 4 . msb of a channel decode that deter-mines which transmit channel data will appear in the tds0m register. see section 9 or details. tcm3 ccr4.3 transmit channel monitor bit 3. tcm2 ccr4.2 transmit channel monitor bit 2. tcm1 ccr4.1 transmit channel monitor bit 1. tcm0 ccr4.0 transmit channel monitor bit 0. lsb of the channel decode. ccr5: common control register 5 (address = aa hex) (msb) (lsb) ? resalgn tesalgn rcm4 rcm3 rcm2 rcm1 rcm0 symbol position name and description ? ccr5.7 not assigned. should be set to zero when written resalgn ccr5.6 receive elastic store align. setting this bit from a zero to a one may force the receive elastic store?s write/read pointers to a minimum separation of half a frame. no action will be taken if the pointer separation is already greater or equal to half a frame. if pointer separation is less then half a frame, the command will be executed and data will be disrupted. should be toggled after rsysclk has been applied and is stable. must be cleared and set again for a subsequent align. see section 13 for details.
ds21q44 33 of 105 symbol position name and description tesalgn ccr5.5 transmit elastic store align. setting this bit from a zero to a one may force the transmit elastic store?s write/read pointers to a minimum separation of half a frame. no action will be taken if the pointer separation is already greater or equal to half a frame. if pointer separation is less then half a frame, the command will be executed and data will be disrupted. should be toggled after tsysclk has been applied and is stable. must be cleared and set again for a subsequent align. see section 13 for details. rcm4 ccr5.4 receive channel monitor bit 4. msb of a channel decode that determines which receive channel data will appear in the rds0m register. see section 9 for details. rcm3 ccr5.3 receive channel monitor bit 3. rcm2 ccr5.2 receive channel monitor bit 2. rcm1 ccr5.1 receive channel monitor bit 1. rcm0 ccr5.0 receive channel monitor bit 0. lsb of the channel decode. ccr6: common control register 6 (address=1d hex) (msb) (lsb) ?????tclksrcresrtesr symbol position name and description ? ccr6.7 not assigned. should be set to zero when written ? ccr6.6 not assigned. should be set to zero when written ? ccr6.5 not assigned. should be set to zero when written ? ccr6.4 not assigned. should be set to zero when written ? ccr6.3 not assigned. should be set to zero when written tclksrc ccr6.2 transmit clock source select. this function allows the user to internally select rclk as the clock source for the transmit side formatter. 0 = transmit side formatter clocked with signal applied at tclk pin. lotc mux function is operational (tcr1.7) 1 = transmit side formatter clocked with rclk. resr ccr6.1 receive elastic store reset. setting this bit from a zero to a one will force the receive elastic store to a depth of one frame. receive data is lost during the reset. should be toggled after rsysclk has been applied and is stable. do not leave this bit set high. tesr ccr6.0 transmit elastic store reset. setting this bit from a zero to a one will force the transmit elastic store to a depth of one frame. transmit data is lost during the reset. should be toggled after tsysclk has been applied and is stable. do not leave this bit set high.
ds21q44 34 of 105 7. status and information registers there is a set of seven registers per framer that contain information on the current real time status of a framer in the ds21q44, status register 1 (sr1), status register 2 (sr2), receive information register (rir), synchronizer status register (ssr) and a set of three registers for the onboard hdlc controller. the specific details on the four registers pertaining to the hdlc controller are covered in section 15 but they operate the same as the other status registers in the ds21q44 and this operation is described below. when a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a one. all of the bits in sr1, sr2, and rir1 registers operate in a latched fashion. the synchronizer status register contents are not latched. this means that if an event or an alarm occurs and a bit is set to a one in any of the registers, it will remain set until the user reads that bit. the bit will be cleared when it is read and it will not be set again until the event has occurred again (or in the case of the rsa1, rsa0, rdma, rua1, rra, rcl, and rlos alarms, the bit will remain set if the alarm is still present). the user will always precede a read of any of the sr1, sr2 and rir registers with a write. the byte written to the register will inform the framer which bits the user wishes to read and have cleared. the user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. when a one is written to a bit location, the read register will be updated with the latest information. when a zero is written to a bit position, the read register will not be updated and the previous value will be held. a write to the status and information registers will be immediately followed by a read of the same register. the read result should be logically and?ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. this second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. this write?read? write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. this operation is key in controlling the ds21q44 with higher?order software languages. the ssr register operates differently than the other three. it is a read only register and it reports the status of the synchronizer in real time. this register is not latched and it is not necessary to precede a read of this register with a write. the sr1, sr2, and hsr registers have the unique ability to initiate a hardware interrupt via the int* output pin. each of the alarms and events in the sr1, sr2, and hsr can be either masked or unmasked from the interrupt pin via the interrupt mask register 1 (imr1), interrupt mask register 2 (imr2), and hdlc interrupt mask register (himr) respectively. the himr register is covered in section 15. the interrupts caused by four of the alarms in sr1 (namely rua1, rra, rcl, and rlos) act differently than the interrupts caused by other alarms and events in sr1 and sr2 (namely rsa1, rdma, rsa0, rslip, rmf, raf, tmf, sec, taf, lotc, rcmf, and tslip). these four alarm interrupts will force the int* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in table 7-1). the int* pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur. if the alarm is still present, the register bit will remain set. the event caused interrupts will force the int* pin low when the event occurs. the int* pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
ds21q44 35 of 105 isr: interrupt status register (any address from 0c0 hex to 0ff hex) (msb) (lsb) f3hdlc f3sr f2hdlc f2sr f1hdlc f1sr f0hdlc f0sr symbol position name and description f3hdlc isr.7 framer 3 hdlc controller interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f3sr isr.6 framer 3 sr1 or sr2 interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f2hdlc isr.5 framer 2 hdlc controller interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f2sr isr.4 framer 2 sr1 or sr2 interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f1hdlc isr.3 framer 1 hdlc controller interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f1sr isr.2 framer 1 sr1 or sr2 interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f0hdlc isr.1 framer 0 hdlc controller interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f0sr isr.0 framer 0 sr1 or sr2 interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending.
ds21q44 36 of 105 rir: receive information register (address=08 hex) (msb) (lsb) tesf tese lorc resf rese crcrc fasrc casrc symbol position name and description tesf rir.7 transmit side elastic store full. set when the transmit side elastic store buffer fills and a frame is deleted. tese rir.6 transmit side elastic store empty. set when the transmit side elastic store buffer empties and a frame is repeated. lorc rir.5 loss of receive clock. set when the rclk pin has not transitioned for at least 2 s (3 s 1 s). resf rir.4 receive side elastic store full. set when the receive side elastic store buffer fills and a frame is deleted. rese rir.3 receive side elastic store empty. set when the receive side elastic store buffer empties and a frame is repeated. crcrc rir.2 crc resync criteria met. set when 915/1000 code words are received in error. fasrc rir.1 fas resync criteria met. set when 3 consecutive fas words are received in error. casrc rir.0 cas resync criteria met. set when 2 consecutive cas mf alignment words are received in error. ssr: synchronizer status register (address=1e hex) (msb) (lsb) csc5 csc4 csc3 csc2 csc0 fassa cassa crc4sa symbol position name and description csc5 ssr.7 crc4 sync counter bit 5. msb of the 6?bit counter. csc4 ssr.6 crc4 sync counter bit 4. csc3 ssr.5 crc4 sync counter bit 3. csc2 ssr.4 crc4 sync counter bit 2. csc0 ssr.3 crc4 sync counter bit 0. lsb of the 6?bit counter. the next to lsb is not accessible. fassa ssr.2 fas sync active. set while the synchronizer is searching for alignment at the fas level. cassa ssr.1 cas mf sync active. set while the synchronizer is searching for the cas mf alignment word. crc4sa ssr.0 crc4 mf sync active. set while the synchronizer is searching for the crc4 mf alignment word.
ds21q44 37 of 105 crc4 sync counter the crc4 sync counter increments each time the 8 ms crc4 multiframe search times out. the counter is cleared when the framer has successfully obtained synchronization at the crc4 level. the counter can also be cleared by disabling the crc4 mode (ccr1.0=0). this counter is useful for determining the amount of time the framer has been searching for synchronization at the crc4 level. itu g.706 suggests that if synchronization at the crc4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action taken. the crc4 sync counter will rollover. sr1: status register 1 (address=06 hex) (msb) (lsb) rsa1 rdma rsa0 rslip rua1 rra rcl rlos symbol position name and description rsa1 sr1.7 receive signaling all ones / signaling change. set when over a full mf, the content of timeslot 16 contains less than three zeros. this alarm is not disabled in the ccs signaling mode. a change in the contents of rs1 through rs16 from one multiframe to the next will cause rsa1 and rsa0 to be set. rdma sr1.6 receive distant mf alarm. set when bit?6 of timeslot 16 in frame 0 has been set for two consecutive multiframes. this alarm is not disabled in the ccs signaling mode. rsa0 sr1.5 receive signaling all zeros / signaling change. set when over a full mf, timeslot 16 contains all zeros. a change in the contents of rs1 through rs16 from one multiframe to the next will cause rsa1 and rsa0 to be set. rslip sr1.4 receive side elastic store slip. set when the elastic store has either repeated or deleted a frame of data. rua1 sr1.3 receive unframed all ones. set when an unframed all ones code is received at rpos and rneg. rra sr1.2 receive remote alarm. set when a remote alarm is received at rpos and rneg. rcl sr1.1 receive carrier loss. set when 255 (or 2048 if ccr3.0=1) consecutive zeros have been detected at rpos and rneg. rlos sr1.0 receive loss of sync. set when the device is not synchronized to the receive e1 stream.
ds21q44 38 of 105 alarm criteria table 7-1 alarm set criteria clear criteria itu spec. rsa1 (receive signaling all ones) over 16 consecutive frames (one full mf) timeslot 16 contains less than three zeros over 16 consecutive frames (one full mf) timeslot 16 contains three or more zeros g.732 4.2 rsa0 (receive signaling all zeros) over 16 consecutive frames (one full mf) timeslot 16 contains all zeros over 16 consecutive frames (one full mf) timeslot 16 contains at least a single one g.732 5.2 rdma (receive distant multiframe alarm) bit 6 in timeslot 16 of frame 0 set to one for two consecutive mf bit 6 in timeslot 16 of frame 0 set to zero for two consecutive mf o.162 2.1.5 rua1 (receive unframed all ones) less than three zeros in two frames (512?bits) more than two zeros in two frames (512?bits) o.162 1.6.1.2 rra (receive remote alarm) bit 3 of non?align frame set to one for three consecutive occasions bit 3 of non?align frame set to zero for three consecutive occasions o.162 2.1.4 rcl (receive carrier loss) 255 (or 2048) consecutive zeros received in 255?bit times, at least 32 ones are received g.775 / g.962 sr2: status register 2 (address=07 hex) (msb) (lsb) rmf raf tmf sec taf lotc rcmf tslip symbol position name and description rmf sr2.7 receive cas multiframe . set every 2 ms (regardless if cas signaling is enabled or not) on receive multiframe boundaries. used to alert the host that signaling data is available. raf sr2.6 receive align frame. set every 250 s at the beginning of align frames. used to alert the host that si and sa bits are available in the raf and rnaf registers. tmf sr2.5 transmit multiframe. set every 2 ms (regardless if crc4 is enabled) on transmit multiframe boundaries. used to alert the host that signaling data needs to be updated. sec sr2.4 one second timer. set on increments of one second based on rclk. if ccr2.7=1, then this bit will be set every 62.5 ms instead of once a second. taf sr2.3 transmit align frame. set every 250 s at the beginning of align frames. used to alert the host that the taf and tnaf registers need to be updated. lotc sr2.2 loss of transmit clock. set when the tclk pin has not transitioned for one channel time (or 3.9 s). will force the lotc pin high if enabled via tcr2.0.
ds21q44 39 of 105 symbol position name and description rcmf sr2.1 receive crc4 multiframe. set on crc4 multiframe boundaries; will continue to be set every 2 ms on an arbitrary boundary if crc4 is disabled. tslip sr2.0 transmit elastic store slip. set when the elastic store has either repeated or deleted a frame of data. imr1: interrupt mask register 1 (address=16 hex) (msb) (lsb) rsa1 rdma rsa0 rslip rua1 rra rcl rlos symbol position name and description rsa1 imr1.7 receive signaling all ones / signaling change. 0=interrupt masked 1=interrupt enabled rdma imr1.6 receive distant mf alarm. 0=interrupt masked 1=interrupt enabled rsa0 imr1.5 receive signaling all zeros / signaling change. 0=interrupt masked 1=interrupt enabled rslip imr1.4 receive elastic store slip occurrence. 0=interrupt masked 1=interrupt enabled rua1 imr1.3 receive unframed all ones. 0=interrupt masked 1=interrupt enabled rra imr1.2 receive remote alarm. 0=interrupt masked 1=interrupt enabled rcl imr1.1 receive carrier loss. 0=interrupt masked 1=interrupt enabled rlos imr1.0 receive loss of sync. 0=interrupt masked 1=interrupt enabled
ds21q44 40 of 105 imr2: interrupt mask register 2 (address=17 hex) (msb) (lsb) rmf raf tmf sec taf lotc rcmf tslip symbol position name and description rmf imr2.7 receive cas multiframe. 0=interrupt masked 1=interrupt enabled raf imr2.6 receive align frame. 0=interrupt masked 1=interrupt enabled tmf imr2.5 transmit multiframe. 0=interrupt masked 1=interrupt enabled sec imr2.4 one second timer. 0=interrupt masked 1=interrupt enabled taf imr2.3 transmit align frame. 0=interrupt masked 1=interrupt enabled lotc imr2.2 loss of transmit clock. 0=interrupt masked 1=interrupt enabled rcmf imr2.1 receive crc4 multiframe. 0=interrupt masked 1=interrupt enabled tslip imr2.0 transmit side elastic store slip occurrence. 0=interrupt masked 1=interrupt enabled 8. error count registers there are a set of four counters in each framer that record bipolar or code violations, errors in the crc4 smf code words, e bits as reported by the far end, and word errors in the fas. each of these four counters are automatically updated on either one second boundaries (ccr2.7=0) or every 62.5 ms (ccr2.7=1) as determined by the timer in status register 2 (sr2.4). hence, these registers contain performance data from either the previous second or the previous 62.5 ms. the user can use the interrupt from the one second timer to determine when to read these registers. the user has a full second (or 62.5 ms) to read the counters before the data is lost. all four counters will saturate at their respective maximum counts and they will not rollover. bpv or code violation counter violation count register 1 (vcr1) is the most significant word and vcr2 is the least significant word of a 16?bit counter that records either bipolar violations (bpvs) or code violations (cvs). if ccr2.6=0, then the vcr counts bipolar violations. bipolar violations are defined as consecutive marks of the same polarity. in this mode, if the hdb3 mode is set for the receive side via ccr1.2, then hdb3 code words are not counted as bpvs. if ccr2.6=1, then the vcr counts code violations as defined in itu o.161.
ds21q44 41 of 105 code violations are defined as consecutive bipolar violations of the same polarity. in most applications, the framer should be programmed to count bpvs when receiving ami code and to count cvs when receiving hdb3 code. this counter increments at all times and is not disabled by loss of sync conditions. the counter saturates at 65,535 and will not rollover. the bit error rate on a e1 line would have to be greater than 10** ?2 before the vcr would saturate. vcr1: upper bipolar violation count register 1 (address=00 hex) vcr2: lower bipolar violation count register 2 (address=01 hex) (msb) (lsb) v15 v14 v13 v12 v11 v10 v9 v8 vcr1 v7 v6 v5 v4 v3 v2 v1 v0 vcr2 symbol position name and description v15 vcr1.7 msb of the 16?bit code violation count v0 vcr2.0 lsb of the 10?bit code violation count crc4 error counter crc4 count register 1 (crccr1) is the most significant word and crccr2 is the least significant word of a 10?bit counter that records word errors in the cyclic redundancy check 4 (crc4). since the maximum crc4 count in a one second period is 1000, this counter cannot saturate. the counter is disabled during loss of sync at either the fas or crc4 level; it will continue to count if loss of multiframe sync occurs at the cas level. crccr1: crc4 count register 1 (address=02 hex) crccr2: crc4 count register 2 (address=03 hex) (msb) (lsb) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) crc9 crc8 crccr1 crc7 crc6 crc5 crc4 crc3 crc2 crc1 crc0 crccr2 symbol position name and description crc9 crccr1.1 msb of the 10?bit crc4 error count crc0 crccr2.0 lsb of the 10?bit crc4 error count note: 1. the upper six bits of crccr1 at address 02 are the most significant bits of the 12?bit fas error counter. e?bit counter e?bit count register 1 (ebcr1) is the most significant word and ebcr2 is the least significant word of a 10?bit counter that records far end block errors (febe) as reported in the first bit of frames 13 and 15 on e1 lines running with crc4 multiframe. these count registers will increment once each time the received e?bit is set to zero. since the maximum e?bit count in a one second period is 1000, this counter cannot saturate. the counter is disabled during loss of sync at either the fas or crc4 level; it will continue to count if loss of multiframe sync occurs at the cas level.
ds21q44 42 of 105 ebcr1: e?bit count register 1 (address=04 hex) ebcr2: e?bit count register 2 (address=05 hex) (msb) (lsb) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) eb9 eb8 ebcr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 ebcr2 symbol position name and description eb9 ebcr1.1 msb of the 10?bit e?bit error count eb0 ebcr2.0 lsb of the 10?bit e?bit error count note: the upper six bits of ebcr1 at address 04 are the least significant bits of the 12?bit fas error counter. fas error counter fas count register 1 (fascr1) is the most significant word and fascr2 is the least significant word of a 12?bit counter that records word errors in the frame alignment signal in timeslot 0. this counter is disabled when rlos is high. fas errors will not be counted when the framer is searching for fas alignment and/or synchronization at either the cas or crc4 multiframe level. since the maximum fas word error count in a one second period is 4000, this counter cannot saturate. fascr1: fas error count register 1 (address=02 hex) fascr2: fas error count register 2 (address=04 hex) (msb) (lsb) fas11 fas10 fas9 fas8 fas7 fas6 (note 2) (note 2) fascr1 fas5 fas4 fas3 fas2 fas1 fas0 (note 1) (note 1) fascr2 symbol position name and description fas11 fascr1.7 msb of the 12?bit fas error count fas0 fascr2.2 lsb of the 12?bit fas error count notes: 1. the lower two bits of fascr1 at address 02 are the most significant bits of the 10?bit crc4 error counter. 2. the lower two bits of fascr2 at address 04 are the most significant bits of the 10?bit e?bit counter.
ds21q44 43 of 105 9. ds0 monitoring function each framer in the ds21q44 has the ability to monitor one ds0 64kbps channel in the transmit direction and one ds0 channel in the receive direction at the same time. in the transmit direction the user will determine which channel is to be monitored by properly setting the tcm0 to tcm4 bits in the ccr4 register. in the receive direction, the rcm0 to rcm4 bits in the ccr5 register need to be properly set. the ds0 channel pointed to by the tcm0 to tcm4 bits will appear in the transmit ds0 monitor (tds0m) register and the ds0 channel pointed to by the rcm0 to rcm4 bits will appear in the receive ds0 (rds0m) register. the tcm4 to tcm0 and rcm4 to rcm0 bits should be programmed with the decimal decode of the appropriate e1 channel. channels 1 through 32 map to register values 0 through 31. for example, if ds0 channel 6 (timeslot 5) in the transmit direction and ds0 channel 15 (timeslot 14) in the receive direction needed to be monitored, then the following values would be programmed into ccr4 and ccr5: tcm4 = 0 rcm4 = 0 tcm3 = 0 rcm3 = 1 tcm2 = 1 rcm2 = 1 tcm1 = 0 rcm1 = 1 tcm0 = 1 rcm0 = 0 ccr4: common control register 4 (address=a8 hex) [repeated here from section 6 for convenience] (msb) (lsb) rlb ? ? tcm4 tcm3 tcm2 tcm1 tcm0 symbol position name and description rlb ccr4.7 remote loopback. 0 = loopback disabled 1 = loopback enabled ? ccr4.6 not assigned. should be set to zero when written. ? ccr4.5 not assigned. should be set to zero when written. tcm4 ccr4.4 transmit channel monitor bit 4 . msb of a channel decode that deter-mines which transmit channel data will appear in the tds0m register. see section 9 or details. tcm3 ccr4.3 transmit channel monitor bit 3. tcm2 ccr4.2 transmit channel monitor bit 2. tcm1 ccr4.1 transmit channel monitor bit 1. tcm0 ccr4.0 transmit channel monitor bit 0. lsb of the channel decode.
ds21q44 44 of 105 tds0m: transmit ds0 monitor register (address=a9 hex) (msb) (lsb) b1 b2 b3 b4 b5 b6 b7 b8 symbol position name and description b1 tds0m.7 transmit ds0 channel bit 1. msb of the ds0 channel (first bit to be transmitted). b2 tds0m.6 transmit ds0 channel bit 2. b3 tds0m.5 transmit ds0 channel bit 3. b4 tds0m.4 transmit ds0 channel bit 4. b5 tds0m.3 transmit ds0 channel bit 5. b6 tds0m.2 transmit ds0 channel bit 6. b7 tds0m.1 transmit ds0 channel bit 7. b8 tds0m.0 transmit ds0 channel bit 8. lsb of the ds0 channel (last bit to be transmitted). ccr5: common control register 5 (address=aa hex) [repeated here from section 6 for convenience] (msb) (lsb) ? resalgn tesalgn rcm4 rcm3 rcm2 rcm1 rcm0 symbol position name and description ? ccr5.7 not assigned. should be set to zero when written resalgn ccr5.6 receive elastic store align. setting this bit from a zero to a one may force the receive elastic store?s write/read pointers to a minimum separation of half a frame. no action will be taken if the pointer separation is already greater or equal to half a frame. if pointer separation is less then half a frame, the command will be executed and data will be disrupted. should be toggled after rsysclk has been applied and is stable. must be cleared and set again for a subsequent align. see section 13 for details. tesalgn ccr5.5 transmit elastic store align. setting this bit from a zero to a one may force the transmit elastic store?s write/read pointers to a minimum separation of half a frame. no action will be taken if the pointer separation is already greater or equal to half a frame. if pointer separation is less then half a frame, the command will be executed and data will be disrupted. should be toggled after tsysclk has been applied and is stable. must be cleared and set again for a subsequent align. see section 13 for details. rcm4 ccr5.4 receive channel monitor bit 4. msb of a channel decode that determines which receive channel data will appear in the rds0m register. see section 9 for details.
ds21q44 45 of 105 symbol position name and description rcm3 ccr5.3 receive channel monitor bit 3. rcm2 ccr5.2 receive channel monitor bit 2. rcm1 ccr5.1 receive channel monitor bit 1. rcm0 ccr5.0 receive channel monitor bit 0. lsb of the channel decode. rds0m: receive ds0 monitor register (address = ab hex) (msb) (lsb) b1 b2 b3 b4 b5 b6 b7 b8 symbol position name and description b1 rds0m.7 receive ds0 channel bit 1. msb of the ds0 channel (first bit to be received). b2 rds0m.6 receive ds0 channel bit 2. b3 rds0m.5 receive ds0 channel bit 3. b4 rds0m.4 receive ds0 channel bit 4. b5 rds0m.3 receive ds0 channel bit 5. b6 rds0m.2 receive ds0 channel bit 6. b7 rds0m.1 receive ds0 channel bit 7. b8 rds0m.0 receive ds0 channel bit 8. lsb of the ds0 channel (last bit to be received). 10. signaling operation each framer in the ds21q44 contains provisions for both processor based (i.e., software based) signaling bit access and for hardware based access. both the processor based access and the hardware based access can be used simultaneously if necessary. the processor based signaling is covered in section 10.1 and the hardware based signaling is covered in section 10.2. 10.1 processor based signaling the channel associated signaling (cas) bits embedded in the e1 stream can be extracted from the receive stream and inserted into the transmit stream by the framer. each of the 30 voice channels has four signaling bits (a/b/c/d) associated with it. the numbers in parenthesis () are the voice channel associated with a particular signaling bit. the voice channel numbers have been assigned as described in the itu documents. please note that this is different than the channel numbering scheme (1 to 32) that is used in the rest of the data sheet. for example, voice channel 1 is associated with timeslot 1 (channel 2) and voice channel 30 is associated with timeslot 31 (channel 32). there is a set of 16 registers for the receive side (rs1 to rs16) and 16 registers on the transmit side (ts1 to ts16). the signaling registers are detailed below.
ds21q44 46 of 105 rs1 to rs16: receive signaling registers (address=30 to 3f hex) (msb) (lsb) 0000 xyxxrs1 (30) a(1) b(1) c(1) d(1) a(16) b(16) c(16) d(16) rs2 (31) a(2) b(2) c(2) d(2) a(17) b(17) c(17) d(17) rs3 (32) a(3) b(3) c(3) d(3) a(18) b(18) c(18) d(18) rs3 (33) a(4) b(4) c(4) d(4) a(19) b(19) c(19) d(19) rs5 (34) a(5) b(5) c(5) d(5) a(20) b(20) c(20) d(20) rs6 (35) a(6) b(6) c(6) d(6) a(21) b(21) c(21) d(21) rs7 (36) a(7) b(7) b(7) b(7) b(22) b(22) b(22) b(22) rs8 (37) a(8) b(8) c(8) d(8) a(23) b(23) c(23) d(23) rs9 (38) a(9) b(9) c(9) d(9) a(24) b(24) c(24) d(24) rs10 (39) a(10) b(10) c(10) d(10) a(25) b(25) c(25) d(25) rs11 (3a) a(11) b(11) c(11) d(11) a(26) b(26) c(26) d(26) rs12 (3b) a(12) b(12) c(12) d(12) a(27) b(27) c(27) d(27) rs13 (3c) a(13) b(13) c(13) d(13) a(28) b(28) c(28) d(28) rs14 (3d) a(14) b(14) c(14) d(14) a(29) b(29) c(29) d(29) rs15 (3e) a(15) b(15) c(15) d(15) a(30) b(30) c(30) d(30) rs16 (3f) symbol position name and description x rs1.0/1/3 spare bits. y rs1.2 remote alarm bit (integrated and reported in sr1.6). a(1) rs2.7 signaling bit a for channel 1 d(30) rs16.0 signaling bit d for channel 30. each receive signaling register (rs1 to rs16) reports the incoming signaling from two timeslots. the bits in the receive signaling registers are updated on multiframe boundaries so the user can utilize the receive multiframe interrupt in the receive status register 2 (sr2.7) to know when to retrieve the signaling bits. the user has a full 2 ms to retrieve the signaling bits before the data is lost. the rs registers are updated under all conditions. their validity should be qualified by checking for synchronization at the cas level. in ccs signaling mode, rs1 to rs16 can also be used to extract signaling information. via the sr2.7 bit, the user will be informed when the signaling registers have been loaded with data. the user has 2 ms to retrieve the data before it is lost. the signaling data reported in rs1 to rs16 is also available at the rsig and rser pins. three status bits in status register 1 (sr1) monitor the contents of registers rs1 through rs16. status monitored includes all zeros detection, all ones detection and a change in register contents. the receive signaling all zeros status bit (sr1.5) is set when over a full multi-frame, rs1 through rs16 contain all zeros. the receive signaling all ones status bit (sr1.7) is set when over a full multi-frame, rs1 through rs16 contain less than three zeros. a change in the contents of rs1 through rs16 from one multiframe to the next will cause rsa1 (sr1.7) and rsa0 (sr1.5) status bits to be set at the same time. the user can enable the int* pin to toggle low upon detection of a change in signaling by setting either the imr1.7 or imr1.5 bit. once a signaling change has been detected, the user has at least 1.75 ms to read the data out of the rs1 to rs16 registers before the data will be lost.
ds21q44 47 of 105 ts1 to ts16: transmit signaling registers (address=40 to 4f hex) (msb) (lsb) 0000 xyxxts1 (40) a(1) b(1) c(1) d(1) a(16) b(16) c(16) d(16) ts2 (41) a(2) b(2) c(2) d(2) a(17) b(17) c(17) d(17) ts3 (42) a(3) b(3) c(3) d(3) a(18) b(18) c(18) d(18) ts4 (43) a(4) b(4) c(4) d(4) a(19) b(19) c(19) d(19) ts5 (44) a(5) b(5) c(5) d(5) a(20) b(20) c(20) d(20) ts6 (45) a(6) b(6) c(6) d(6) a(21) b(21) c(21) d(21) ts7 (46) a(7) b(7) b(7) b(7) b(22) b(22) b(22) b(22) ts8 (47) a(8) b(8) c(8) d(8) a(23) b(23) c(23) d(23) ts9 (48) a(9) b(9) c(9) d(9) a(24) b(24) c(24) d(24) ts10 49) a(10) b(10) c(10) d(10) a(25) b(25) c(25) d(25) ts11(4a) a(11) b(11) c(11) d(11) a(26) b(26) c(26) d(26) ts12 (4b) a(12) b(12) c(12) d(12) a(27) b(27) c(27) d(27) ts13 (4c) a(13) b(13) c(13) d(13) a(28) b(28) c(28) d(28) ts14 (4d) a(14) b(14) c(14) d(14) a(29) b(29) c(29) d(29) ts15 (4e) a(15) b(15) c(15) d(15) a(30) b(30) c(30) d(30) ts16 (4f) symbol position name and description x ts1.0/1/3 spare bits. y ts1.2 remote alarm bit (integrated and reported in sr1.6). a(1) ts2.7 signaling bit a for channel 1 d(30) ts16.0 signaling bit d for channel 30. each transmit signaling register (ts1 to ts16) contains the cas bits for two timeslots that will be inserted into the outgoing stream if enabled to do so via tcr1.5. on multiframe boundaries, the framer will load the values present in the transmit signaling register into an outgoing signaling shift register that is internal to the device. the user can utilize the transmit multiframe bit in status register 2 (sr2.5) to know when to update the signaling bits. the bit will be set every 2 ms and the user has 2 ms to update the tsr?s before the old data will be retransmitted. itu specifications recommend that the abcd signaling not be set to all zeros because they will emulate a cas multiframe alignment word. the ts1 register is special because it contains the cas multiframe alignment word in its upper nibble. the upper nibble must always be set to 0000 or else the terminal at the far end will lose multiframe synchronization. if the user wishes to transmit a multiframe alarm to the far end, then the ts1.2 bit should be set to a one. if no alarm is to be transmitted, then the ts1.2 bit should be cleared. the three remaining bits in ts1 are the spare bits. if they are not used, they should be set to one. in ccs signaling mode, ts1 to ts16 can also be used to insert signaling information. via the sr2.5 bit, the user will be informed when the signaling registers need to be loaded with data. the user has 2 ms to load the data before the old data will be retransmitted. via the ccr3.6 bit, the user has the option to use the transmit channel blocking registers (tcbrs) to deter-mine on a channel by channel basis, which signaling bits are to be inserted via the tsrs (the corresponding bit in the tcbrs=1) and which are to be sourced from the tser or tsig pin (the corresponding bit in the tcbrs=0). see the transmit data flow diagram in section 18 for more details.
ds21q44 48 of 105 10.2 hardware based signaling receive side in the receive side of the hardware based signaling, there are two operating modes for the signaling buffer; signaling extraction and signaling re?insertion. signaling extraction involves pulling the signaling bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in a serial pcm fashion on a channel?by?channel basis at the rsig output. this mode is always enabled. in this mode, the receive elastic store may be enabled or disabled. if the receive elastic store is enabled, then the backplane clock (rsysclk) must be 2.048 mhz. the abcd signaling bits are output on rsig in the lower nibble of each channel. the rsig data is updated once a multiframe (2 ms) unless a freeze is in effect. see the timing diagrams in section 18 for some examples. the other hardware based signaling operating mode called signaling re?insertion can be invoked by setting the rsre control bit high (ccr3.3=1). in this mode, the user will provide a multiframe sync at the rsync pin and the signaling data be re?aligned at the rser output according to this applied multiframe boundary. in this mode, the elastic store must be enabled the backplane clock must be 2.048 mhz. the signaling data in the two multiframe buffer will be frozen in a known good state upon either a loss of synchronization (oof event), carrier loss, or frame slip. to allow this freeze action to occur, the rfe control bit (ccr2.0) should be set high. the user can force a freeze by setting the rff control bit (ccr2.1) high. setting the rff bit high causes the same freezing action as if a loss of synchronization, carrier loss, or slip has occurred. the 2 multiframe buffer provides an approximate 1 multiframe delay in the signaling bits provided at the rsig pin (and at the rser pin if rsre=1 via ccr3.3). when freezing is enabled (rfe=1), the signaling data will be held in the last known good state until the corrupting error condition subsides. when the error condition sub-sides, the signaling data will be held in the old state for an additional 3 ms to 5 ms before being allowed to be updated with new signaling data. transmit side via the thse control bit (ccr3.2), the ds21q44 can be set up to take the signaling data presented at the tsig pin and insert the signaling data into the pcm data stream that is being input at the tser pin. the hardware signaling insertion capabilities of each framer are available whether the transmit side elastic store is enabled or disabled. if the transmit side elastic store is enabled, the backplane clock (tsysclk) must be 2.048 mhz. when hardware signaling insertion is enabled on a framer (thse=1), then the user must enable the transmit channel blocking register function select (tcbfs) control bit (ccr3.6=1). this is needed so that the cas multiframe alignment word, multiframe remote alarm, and spare bits can be added to timeslot 16 in frame 0 of the multiframe. the ts1 register should be programmed with the proper information. if ccr3.6=1, then a zero in the tcbrs implies that signaling data is to be sourced from tser (or tsig if ccr3.2=1) and a one implies that signaling data for that channel is to be sourced from the transmit signaling (ts) registers. see definition below.
ds21q44 49 of 105 tcbr1/tcbr2/tcbr3/tcbr4: definition when ccr3.6=1 (msb) (lsb) ch20 ch4 ch19 ch3 ch18 ch2 ch17* ch1* tcbr1 (22) ch24 ch8 ch23 ch7 ch22 ch6 ch21 ch5 tcbr2 (23) ch28 ch12 ch27 ch11 ch26 ch10 ch25 ch9 tcbr3 (24) ch32 ch16 ch31 ch15 ch30 ch14 ch29 ch13 tcbr4 (25) note: *=ch1 and ch17 should be set to one to allow the internal ts1 register to create the cas multiframe alignment word and spare/remote alarm bits. the user can also take advantage of this functionality to intermix signaling data from the tsig pin and from the internal transmit signaling registers (ts1 to ts16). as an example, assume that the user wishes to source all the signaling data except for voice channels 5 and 10 from the tsig pin. in this application, the following bits and registers would be programmed as follows: control bits register values thse=1 (ccr3.2) ts1=0bh (mf alignment word, remote alarm etc.) tcbfs=1 (ccr3.6) tcbr1=03h (source timeslot 16, frame 1 data) t16s=1(tcr1.5) tcbr2=01h (source voice channel 5 signaling data from ts6) tcbr3=04h (source voice channel 10 signaling data from ts11) tcbr4=00h 11. per?channel code generation and loopback each framer in the ds21q44 can replace data on a channel?by?channel basis in both the transmit and receive directions. the transmit direction is from the backplane to the e1 line and is covered in section 11.1. the receive direction is from the e1 line to the backplane and is covered in section 11.2. 11.1 transmit side code generation in the transmit direction there are two methods by which channel data from the backplane can be overwritten with data generated by the framer. the first method which is covered in section 11.1.1 was a feature contained in the original ds21q43 while the second method which is covered in section 11.1.2 is a new feature of the ds21q44. 11.1.1 simple idle code insertion and per?channel loopback the first method involves using the transmit idle registers (tir1/2/3/4) to determine which of the 32 e1 channels should be overwritten with the code placed in the transmit idle definition register (tidr). this method allows the same 8?bit code to be placed into any of the 32 e1 channels. if this method is used, then the ccr3.5 control bit must be set to zero. each of the bit position in the transmit idle registers (tir1/tir2/tir3/tir4) represent a ds0 channel in the outgoing frame. when these bits are set to a one, the corresponding channel will transmit the idle code contained in the transmit idle definition register (tidr).
ds21q44 50 of 105 the transmit idle registers (tirs) have an alternate function that allow them to define a per?channel loopback (pclb). if the tirfs control bit (ccr3.5) is set to one, then the tirs will determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the e1 line. if this mode is enabled, then transmit and receive clocks and frame syncs must be synchronized. one method to accomplish this would be to tie rclk to tclk and rfsync to tsync. there are no restrictions on which channels can be looped back or on how many channels can be looped back. tir1/tir2/tir3: transmit idle registers (address=26 to 29 hex) [also used for per?channel loopback] (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 tir1 (26) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 tir2 (27) ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 tir3 (28) ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 tir4 (29) symbols positions name and description ch1 - 32 tir1.0 - 4.7 transmit idle code insertion control bits. 0 = do not insert the idle code in the tidr into this channel 1 = insert the idle code in the tidr into this channel notes: if ccr3.5=1, then a zero in the tirs implies that channel data is to be sourced from tser and a one implies that channel data is to be sourced from the output of the receive side framer (i.e., per?channel loopback; see figure 1?1). tidr: transmit idle definition register (address=2a hex) (msb) (lsb) tidr7 tidr6 tidr5 tidr4 tidr3 tidr2 tidr1 tidr0 symbol position name and description tidr7 tidr.7 msb of the idle code (this bit is transmitted first) tidr0 tidr.0 lsb of the idle code (this bit is transmitted last) 11.1.2 per?channel code insertion the second method involves using the transmit channel control registers (tcc1/2/3/4) to determine which of the 32 e1 channels should be overwritten with the code placed in the transmit channel registers (tc1 to tc32). this method is more flexible than the first in that it allows a different 8?bit code to be placed into each of the 32 e1 channels.
ds21q44 51 of 105 tc1 to tc32: transmit channel registers (address=60 to 7f hex) (for brevity, only channel one is shown; see table 4-1 for other register address) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 tc1 (60) symbol position name and description c7 tc1.7 msb of the code (this bit is transmitted first) c0 tc1.0 lsb of the code (this bit is transmitted last) tcc1/tcc2/tcc3/tcc4: transmit channel control register (address=a0 to a3 hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 tcc1 (a0) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 tcc2 (a1) ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 tcc3 (a2) ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 tcc4 (a3) symbol position name and description ch1 - 32 tcc1.0 - 4.7 transmit code insertion control bits 0 = do not insert data from the tc register into the transmit data stream 1 = insert data from the tc register into the transmit data stream 11.2 receive side code generation on the receive side, the receive channel control registers (rcc1/2/3/4) are used to determine which of the 32 e1 channels off of the e1 line and going to the backplane should be overwritten with the code placed in the receive channel registers (rc1 to rc32). this method allows a different 8?bit code to be placed into each of the 32 e1 channels. rc1 to rc32: receive channel registers (address=80 to 9f hex) (for brevity, only channel one is shown; see table 4-1 for other register address) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 rc1 (80) symbol position name and description c7 rc1.7 msb of the code (this bit is sent first to the backplane) c0 rc1.0 lsb of the code (this bit is sent last to the backplane)
ds21q44 52 of 105 rcc1/rcc2/rcc3/rcc4: receive channel control register (address = a4 to a7 hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rcc1 (a4) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rcc2 (a5) ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 rcc3 (a6) ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 rcc4 (a7) symbol position name and description ch1 - 32 rcc1.0 - 4.7 receive code insertion control bits 0 = do not insert data from the rc register into the receive data stream 1 = insert data from the rc register into the receive data stream 12. clock blocking registers the receive channel blocking registers (rcbr1 / rcbr2 / rcbr3 / rcbr4) and the transmit channel blocking registers (tcbr1 / tcbr2 / tcbr3 / tcbr4) control rchblk and tchblk pins respectively. (the rchblk and tchblk pins are user programmable outputs that can be forced either high or low during individual channels). these outputs can be used to block clocks to a usart or lapd controller in isdn?pri applications. when the appropriate bits are set to a one, the rchblk and tchblk pin will be held high during the entire corresponding channel time. see the timing in section 18 for an example. the tcbrs have alternate mode of use. via the ccr3.6 bit, the user has the option to use the tcbrs to determine on a channel by channel basis, which signaling bits are to be inserted via the tsrs (the corresponding bit in the tcbrs=1) and which are to be sourced from the tser or tsig pins (the corresponding bit in the tcbr=0). see the timing in section 18 for an example. rcbr1/rcbr2/rcbr3/rcbr4: receive channel blocking registers (address=2b to 2e hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rcbr1 (2b) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rcbr2 (2c) ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 rcbr3 (2d) ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 rcbr4 (2e) symbols positions name and description ch1 - 32 rcbr1.0 - 4.7 receive channel blocking control bits. 0 = force the rchblk pin to remain low during this channel time 1 = force the rchblk pin high during this channel time
ds21q44 53 of 105 tcbr1/tcbr2/tcbr3/tcbr4: transmit channel blocking registers (address=22 to 25 hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 tcbr1 (22) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 tcbr2 (23) ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 tcbr3 (24) ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 tcbr4 (25) symbols positions name and description ch1 - 32 tcbr1.0 - 4.7 transmit channel blocking control bits. 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time note: if ccr3.6=1, then a zero in the tcbrs implies that signaling data is to be sourced from tser (or tsig if ccr3.2=1) and a one implies that signaling data for that channel is to be sourced from the transmit signaling (ts) registers. see definition below. tcbr1/tcbr2/tcbr3/tcbr4: definition when ccr3.6=1 (msb) (lsb) ch20 ch4 ch19 ch3 ch18 ch2 ch17* ch1* tcbr1 (22) ch24 ch8 ch23 ch7 ch22 ch6 ch21 ch5 tcbr2 (23) ch28 ch12 ch27 ch11 ch26 ch10 ch25 ch9 tcbr3 (24) ch32 ch16 ch31 ch15 ch30 ch14 ch29 ch13 tcbr4 (25) *=ch1 and ch17 should be set to one to allow the internal ts1 register to create the cas multiframe alignment word and spare/remote alarm bits. 13. elastic stores operation each framer in the ds21q44 contains dual two?frame (512 bits) elastic stores, one for the receive direction, and one for the transmit direction. these elastic stores have two main purposes. first, they can be used to rate convert the e1 data stream to 1.544 mbps (or a multiple of 1.544 mbps) which is the t1 rate. secondly, they can be used to absorb the differences in frequency and phase between the e1 data stream and an asynchronous (i.e., not frequency locked) backplane clock which can be 1.544 mhz or 2.048 mhz. the backplane clock can burst at rates up to 8.192 mhz. both elastic stores contain full controlled slip capability which is necessary for this second purpose. both elastic stores within a framer are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to them. the transmit side elastic store can be enabled whether the receive elastic store is enabled or disabled and vice versa. also, each elastic store can interface to either a 1.544 mhz or 2.048 mhz backplane without regard to the backplane rate the other elastic store is interfacing. two mechanisms are available to the user for resetting the elastic stores. the elastic store reset (ccr6.0 & ccr6.1) function forces the elastic stores to a depth of one frame unconditionally. data is lost during the reset. the second method, the elastic store align ( ccr5.5 & ccr5.6) forces the elastic store depth to a minimum depth of half a frame only if the current pointer separation is already less then half a frame. if a realignment occurs data is lost. in both mechanisms, independent resets are provided for both the receive and transmit elastic stores.
ds21q44 54 of 105 13.1 receive side if the receive side elastic store is enabled (rcr2.1=1), then the user must provide either a 1.544 mhz (rcr2.2 =0) or 2.048 mhz (rcr2.2=1) clock at the rsysclk pin. the user has the option of either providing a frame/multiframe sync at the rsync pin (rcr1.5=1) or having the rsync pin provide a pulse on frame/multiframe boundaries (rcr1.5=0). if the user wishes to obtain pulses at the frame boundary, then rcr1.6 must be set to zero and if the user wishes to have pulses occur at the multiframe boundary, then rcr1.6 must be set to one. the ds21q44 will always indicate frame boundaries via the rfsync output whether the elastic store is enabled or not. if the elastic store is enabled, then either cas (rcr1.7=0) or crc4 (rcr1.7=1) multiframe boundaries will be indicated via the rmsync output. if the user selects to apply a 1.544 mhz clock to the rsysclk pin, then every fourth channel of the received e1 data will be deleted and a f?bit position (which will be forced to one) will be inserted. hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted from the received e1 data stream. also, in 1.544 mhz applications, the rchblk output will not be active in channels 25 through 32 (or in other words, rcbr4 is not active). see section 18 for timing details. if the 512?bit elastic buffer either fills or empties, a controlled slip will occur. if the buffer empties, then a full frame of data (256?bits) will be repeated at rser and the sr1.4 and rir.3 bits will be set to a one. if the buffer fills, then a full frame of data will be deleted and the sr1.4 and rir.4 bits will be set to a one. 13.2 transmit side the operation of the transmit elastic store is very similar to the receive side. the transmit side elastic store is enabled via ccr3.7. a 1.544 mhz (ccr3.1=0) or 2.048 mhz (ccr3.1=1) clock can be applied to the tsysclk input. the tsysclk can be a bursty clock with rates up to 8.192 mhz. if the user selects to apply a 1.544 mhz clock to the tsysclk pin, then the data sampled at tser will be ignored every fourth channel. hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be ignored. the user must supply a 8 khz frame sync pulse to the tssync input. see section 18 for timing details. controlled slips in the transmit elastic store are reported in the sr2.0 bit and the direction of the slip is reported in the rir.6 and rir.7 bits. 14. additional (sa) and international (si) bit operation each framer in the ds21q44 provides for access to both the sa and the si bits via three different methods. the first is via a hardware scheme using the rlink/rlclk and tlink/ tlclk pins. the first method is discussed in section 14.1. the second involves using the internal raf/rnaf and taf/tnaf registers and is discussed in section 14.2 the third method which is covered in section 14.3 involves an expanded version of the second method and is one of the features added to the ds21q44 from the original ds21q43 definition. 14.1 hardware scheme on the receive side, all of the received data is reported at the rlink pin. via rcr2, the user can control the rlclk pin to pulse during any combination of sa bits. this allows the user to create a clock that can be used to capture the needed sa bits. if rsync is programmed to output a frame boundary, it will identify the si bits. see section 18 for detailed timing. on the transmit side, the individual sa bits can be either sourced from the internal tnaf register (see section 14.2 for details) or from the external tlink pin. via tcr2, the framer can be programmed to source any combination of the additional bits from the tlink pin. if the user wishes to pass the sa bits through the framer without them being altered, then the device should be set up to source all five sa bits via the tlink pin and the tlink pin should be tied to the tser pin. si bits can be inserted through the tser pin via the clearing of the tcr1.3 bit. please see the timing diagrams and the transmit data flow diagram in section 18 for examples.
ds21q44 55 of 105 14.2 internal register scheme based on double?frame on the receive side, the raf and rnaf registers will always report the data as it received in the additional and international bit locations. the raf and rnaf registers are updated with the setting of the receive align frame bit in status register 2 (sr2.6). the host can use the sr2.6 bit to know when to read the raf and rnaf registers. it has 250 us to retrieve the data before it is lost. on the transmit side, data is sampled from the taf and tnaf registers with the setting of the transmit align frame bit in status register 2 (sr2.3). the host can use the sr2.3 bit to know when to update the taf and tnaf registers. it has 250 us to update the data or else the old data will be retransmitted. data in the si bit position will be overwritten if the framer is programmed: (1) to source the si bits from the tser pin, (2) in the crc4 mode, or (3) have automatic e?bit insertion enabled. data in the sa bit position will be overwritten if any of the tcr2.3 to tcr2.7 bits are set to one (please see section 14.1 for details). please see the register descriptions for tcr1 and tcr2 and the transmit data flow diagram in section 14 for more details. raf: receive align frame register (address=2f hex) (msb) (lsb) si0011011 symbol position name and description si raf.7 international bit. 0raf.6 frame alignment signal bit. 0raf.5 frame alignment signal bit. 1raf.4 frame alignment signal bit. 1raf.3 frame alignment signal bit. 0raf.2 frame alignment signal bit. 1raf.1 frame alignment signal bit 1raf.0 frame alignment signal bit.
ds21q44 56 of 105 rnaf: receive non?align frame register (address=1f hex) (msb) (lsb) si 1 a sa4 sa5 sa6 sa7 sa8 symbol position name and description si rnaf.7 international bit. 1 rnaf.6 frame non?alignment signal bit. a rnaf.5 remote alarm. sa4 rnaf.4 additional bit 4. sa5 rnaf.3 additional bit 5. sa6 rnaf.2 additional bit 6. sa7 rnaf.1 additional bit 7. sa8 rnaf.0 additional bit 8. taf: transmit align frame register (address=20 hex) (msb) (lsb) si0011011 [must be programmed with the seven bit fas word; the ds21q44 does not automatically set these bits] symbol position name and description si taf.7 international bit. 0taf.6 frame alignment signal bit. 0taf.5 frame alignment signal bit. 1taf.4 frame alignment signal bit. 1taf.3 frame alignment signal bit. 0taf.2 frame alignment signal bit. 1taf.1 frame alignment signal bit. 1taf.0 frame alignment signal bit.
ds21q44 57 of 105 tnaf: transmit non?align frame register (address=21 hex) (msb) (lsb) si 1 a sa4 sa5 sa6 sa7 sa8 [bit 2 must be programmed to one; the ds21q44 does not automatically set this bit] symbol position name and description si tnaf.7 international bit. 1 tnaf.6 frame non?alignment signal bit. a tnaf.5 remote alarm (used to transmit the alarm). sa4 tnaf.4 additional bit 4. sa5 tnaf.3 additional bit 5. sa6 tnaf.2 additional bit 6. sa7 tnaf.1 additional bit 7. sa8 tnaf.0 additional bit 8. 14.3 internal register scheme based on crc4 multiframe on the receive side, there is a set of eight registers (rsiaf, rsinaf, rra, rsa4 to rsa8) that report the si and sa bits as they are received. these registers are updated with the setting of the receive crc4 multiframe bit in status register 2 (sr2.1). the host can use the sr2.1 bit to know when to read these registers. the user has 2 ms to retrieve the data before it is lost. the msb of each register is the first received. please see the register descriptions below and the transmit data flow diagram in section 18 for more details. on the transmit side, there is also a set of eight registers (tsiaf, tsinaf, tra, tsa4 to tsa8) that via the transmit sa bit control register (tsacr), can be programmed to insert both si and sa data. data is sampled from these registers with the setting of the transmit multiframe bit in status register 2 (sr2.5). the host can use the sr2.5 bit to know when to update these registers. it has 2 ms to update the data or else the old data will be retransmitted. the msb of each register is the first bit transmitted. please see the register descriptions below and the transmit data flow diagram in section 18 for more details.
ds21q44 58 of 105 register name address (hex) function rsiaf 58 the eight si bits in the align frame. rsinaf 59 the eight si bits in the non?align frame. rra 5a the eight reportings of the receive remote alarm (ra). rsa4 5b the eight sa4 reported in each crc4 multiframe. rsa5 5c the eight sa5 reported in each crc4 multiframe. rsa6 5d the eight sa6 reported in each crc4 multiframe. rsa7 5e the eight sa7 reported in each crc4 multiframe. rsa8 5f the eight sa8 reported in each crc4 multiframe. tsiaf 50 the eight si bits to be inserted into the align frame. tsinaf 51 the eight si bits to be inserted into the non?align frame. tra 52 the eight settings of remote alarm (ra). tsa4 53 the eight sa4 settings in each crc4 multiframe. tsa5 54 the eight sa5 settings in each crc4 multiframe. tsa6 55 the eight sa6 settings in each crc4 multiframe. tsa7 56 the eight sa7 settings in each crc4 multiframe. tsa8 57 the eight sa8 settings in each crc4 multiframe. tsacr: transmit sa bit control register (address=1c hex) (msb) (lsb) siaf sinaf ra sa4 sa5 sa6 sa7 sa8 symbol position name and description siaf tsacr.7 international bit in align frame insertion control bit. 0=do not insert data from the tsiaf register into the transmit data stream. 1=insert data from the tsiaf register into the transmit data stream. sinaf tsacr.6 international bit in non?align frame insertion control bit. 0=do not insert data from the tsinaf register into the transmit data stream. 1=insert data from the tsinaf register into the transmit data stream. ra tsacr.5 remote alarm insertion control bit. 0=do not insert data from the tra register into the transmit data stream. 1=insert data from the tra register into the transmit data stream. sa4 tsacr.4 additional bit 4 insertion control bit. 0=do not insert data from the tsa4 register into the transmit data stream. 1=insert data from the tsa4 register into the transmit data stream.
ds21q44 59 of 105 symbol position name and description sa5 tsacr.3 additional bit 5 insertion control bit. 0=do not insert data from the tsa5 register into the transmit data stream. 1=insert data from the tsa5 register into the transmit data stream. sa6 tsacr.2 additional bit 6 insertion control bit. 0=do not insert data from the tsa6 register into the transmit data stream. 1=insert data from the tsa6 register into the transmit data stream. sa7 tsacr.1 additional bit 7 insertion control bit. 0=do not insert data from the tsa7 register into the transmit data stream. 1=insert data from the tsa7 register into the transmit data stream. sa8 tsacr.0 additional bit 8 insertion control bit. 0=do not insert data from the tsa8 register into the transmit data stream. 1=insert data from the tsa8 register into the transmit data stream. 15. hdlc controller for the sa bits or ds0 each framer in the ds21q44 has the ability to extract/insert data from/ into the sa bit positions (sa4 to sa8) or from/to any multiple of ds0 channels each framer contains a complete hdlc controller and this operation is covered in section 15.1. 15.1 general overview each framer contains a complete hdlc controller with 64?byte buffers in both the transmit and receive directions. the hdlc controller performs all the necessary overhead for generating and receiving a hdlc formatted message. the hdlc controller automatically generates and detects flags, generates and checks the crc check sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the hdlc data stream. there are eleven registers that the host will use to operate and control the operation of the hdlc controller. a brief description of the registers is shown in table 15-1.
ds21q44 60 of 105 hdlc controller register list table 15-1 name function hdlc control register (hcr) general control over the hdlc controller hdlc status register (hsr) key status information for both transmit and receive directions hdlc interrupt mask register (himr) allows/stops status bits to/from causing an interrupt receive hdlc information register (rhir) status information on receive hdlc controller receive hdlc fifo register (rhfr) access to 64?byte hdlc fifo in receive direction receive hdlc ds0 control register 1 (rdc1) receive hdlc ds0 control register 2 (rdc2) controls the hdlc function when used on ds0 channels transmit hdlc information register (thir) status information on transmit hdlc controller transmit hdlc fifo register (thfr) access to 64?byte hdlc fifo in transmit direction transmit hdlc ds0 control register 1 (tdc1) transmit hdlc ds0 control register 2 (tdc2) controls the hdlc function when used on ds0 channels 15.2 hdlc status registers three of the hdlc controller registers (hsr, rhir, and thir) provide status information. when a particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. some of the bits in these three status registers are latched and some are real time bits that are not latched. section 15.4 contains register descriptions that list which bits are latched and which are not. with the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads that bit. the bit will be cleared when it is read and it will not be set again until the event has occurred again. the real time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched. like the other status registers in the framer, the user will always proceed a read of any of the three registers with a write. the byte written to the register will inform the framer which of the latched bits the user wishes to read and have cleared (the real time bits are not affected by writing to the status register). the user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. when a one is written to a bit location, the read register will be updated with current value and it will be cleared. when a zero is written to a bit position, the read register will not be updated and the previous value will be held. a write to the status and information registers will be immediately followed by a read of the same register. the read result should be logically and?ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. this second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. this write?read?write (for polled driven access) or write?read (for interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll
ds21q44 61 of 105 certain bits without disturbing the other bits in the register. this operation is key in controlling the ds21q44 with higher?order software languages. like the sr1 and sr2 status registers, the hsr register has the unique ability to initiate a hardware interrupt via the int* output pin. each of the events in the hsr can be either masked or unmasked from the interrupt pin via the hdlc interrupt mask register (himr). interrupts will force the int* pin low when the event occurs. the int* pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. 15.3 basic operation details as a basic guideline for interpreting and sending hdlc messages, the following sequences can be applied: receive a hdlc message 1. enable rps interrupts. 2. wait for interrupt to occur. 3. disable rps interrupt and enable either rpe, rne, or rhalf interrupt. 4. read rhir to obtain rempty status. a. if rempty=0, then record obyte, cbyte, and pok bits and then read the fifo a1. if cbyte=0 then skip to step 5 a2. if cbyte=1 then skip to step 7 b. if rempty=1, then skip to step 6 5. repeat step 4. 6. wait for interrupt, skip to step 4. 7. if pok=0, then discard whole packet, if pok=1, accept the packet. 8. disable rpe, rne, or rhalf interrupt, enable rps interrupt and return to step 1. transmit a hdlc message 1. make sure hdlc controller is done sending any previous messages and is current sending flags by checking that the fifo is empty by reading the tempty status bit in the thir register. 2. enable either the thalf or tnf interrupt. 3. read thir to obtain tfull status. a. if tfull=0, then write a byte into the fifo and skip to next step (special case occurs when the last byte is to be written, in this case set teom=1 before writing the byte and then skip to step 6) b. if tfull=1, then skip to step 5 4. repeat step 3. 5. wait for interrupt, skip to step 3. 6. disable thalf or tnf interrupt and enable tmend interrupt. 7. wait for an interrupt, then read tudr status bit to make sure packet was transmitted correctly.
ds21q44 62 of 105 15.4 hdlc register description hcr: hdlc control register (address=b0 hex) (msb) (lsb) ? rhr tfs thr tabt teom tzsd tcrcd symbol position name and description ? hcr.7 not assigned. should be set to zero. rhr hcr.6 receive hdlc reset. a 0 to 1 transition will reset the receive hdlc controller. must be cleared and set again for a subsequent reset. tfs hcr.5 transmit flag/idle select. 0 = 7eh. 1 = ffh. thr hcr.4 transmit hdlc reset. a 0 to 1 transition will reset the transmit hdlc controller. must be cleared and set again for a subsequent reset. tabt hcr.3 transmit abort. a 0 to 1 transition will cause the fifo contents to be dumped and one feh abort to be sent followed by 7eh or ffh flags/idle until a new packet is initiated by writing new data into the fifo. must be cleared and set again for a subsequent abort to be sent. teom hcr.2 transmit end of message. should be set to a one just before the last data byte of a hdlc packet is written into the transmit fifo at thfr. the hdlc controller will clear this bit when the last byte has been transmitted. tzsd hcr.1 transmit zero stuffer defeat. overrides internal enable. 0 = enable the zero stuffer (normal operation). 1 = disable the zero stuffer. tcrcd hcr.0 transmit crc defeat. 0 = enable crc generation (normal operation). 1 = disable crc generation.
ds21q44 63 of 105 hsr: hdlc status register (address=b1 hex) (msb) (lsb) ? rpe rps rhalf rne thalf tnf tmend symbol position name and description ?hsr.7 not assigned. should be set to zero. rpe hsr.6 receive packet end. set when the hdlc controller detects either the finish of a valid message (i.e., crc check complete) or when the controller has experienced a message fault such as a crc checking error, or an overrun condition, or an abort has been seen. the setting of this bit prompts the user to read the rhir register for details. rps hsr.5 receive packet start . set when the hdlc controller detects an opening byte. the setting of this bit prompts the user to read the rhir register for details. rhalf hsr.4 receive fifo half full. set when the receive 64?byte fifo fills beyond the half way point. the setting of this bit prompts the user to read the rhir register for details. rne hsr.3 receive fifo not empty. set when the receive 64?byte fifo has at least one byte available for a read. the setting of this bit prompts the user to read the rhir register for details. thalf hsr.2 transmit fifo half empty. set when the transmit 64?byte fifo empties beyond the half way point. the setting of this bit prompts the user to read the thir register for details. tnf hsr.1 transmit fifo not full. set when the transmit 64?byte fifo has at least one byte available. the setting of this bit prompts the user to read the thir register for details. tmend hsr.0 transmit message end. set when the transmit hdlc controller has finished sending a message. the setting of this bit prompts the user to read the thir register for details. note: the rpe, rps, and tmend bits are latched and will be cleared when read.
ds21q44 64 of 105 himr: hdlc interrupt mask register (address=b2 hex) (msb) (lsb) ? rpe rps rhalf rne thalf tnf tmend symbol position name and description ?himr.7 not assigned. should be set to zero. rpe himr.6 receive packet end. 0 = interrupt masked. 1 = interrupt enabled. rps himr.5 receive packet start. 0 = interrupt masked. 1 = interrupt enabled. rhalf himr.4 receive fifo half full. 0 = interrupt masked. 1 = interrupt enabled. rne himr.3 receive fifo not empty. 0 = interrupt masked. 1 = interrupt enabled. thalf himr.2 transmit fifo half empty. 0 = interrupt masked. 1 = interrupt enabled. tnf himr.1 transmit fifo not full. 0 = interrupt masked. 1 = interrupt enabled. tmend himr.0 transmit message end. 0 = interrupt masked. 1 = interrupt enabled.
ds21q44 65 of 105 rhir: receive hdlc information register (address=b3 hex) (msb) (lsb) rabt rcrce rovr rvm rempty pok cbyte obyte symbol position name and description rabt rhir.7 abort sequence detected. set whenever the hdlc controller sees 7 or more ones in a row. rcrce rhir.6 crc error. set when the crc checksum is in error. rovr rhir.5 overrun. set when the hdlc controller has attempted to write a byte into an already full receive fifo. rvm rhir.4 valid message. set when the hdlc controller has detected and checked a complete hdlc packet. rempty rhir.3 empty. a real?time bit that is set high when the receive fifo is empty. pok rhir.2 packet ok. set when the byte available for reading in the receive fifo at rhfr is the last byte of a valid message (and hence no abort was seen, no overrun occurred, and the crc was correct). cbyte rhir.1 closing byte. set when the byte available for reading in the receive fifo at rfdl is the last byte of a message (whether the message was valid or not). obyte rhir.0 opening byte. set when the byte available for reading in the receive fifo at rhfr is the first byte of a message. note: the rabt, rcrce, rovr, and rvm bits are latched and will be cleared when read. rhfr: receive hdlc fifo register (address=b4 hex) (msb) (lsb) hdlc7 hdlc6 hdlc5 hdlc4 hdlc3 hdlc2 hdlc1 hdlc0 symbol position name and description hdlc7 rhfr.7 hdlc data bit 7 . msb of a hdlc packet data byte. hdlc6 rhfr.6 hdlc data bit 6. hdlc5 rhfr.5 hdlc data bit 5. hdlc4 rhfr.4 hdlc data bit 4. hdlc3 rhfr.3 hdlc data bit 3. hdlc2 rhfr.2 hdlc data bit 2. hdlc1 rhfr.1 hdlc data bit 1. hdlc0 rhfr.0 hdlc data bit 0. lsb of a hdlc packet data byte.
ds21q44 66 of 105 thir: transmit hdlc information register (address=b6 hex) (msb) (lsb) ?????emptytfulltudr symbol position name and description ?thir.7 not assigned. could be any value when read. ?thir.6 not assigned. could be any value when read. ?thir.5 not assigned. could be any value when read. ?thir.4 not assigned. could be any value when read. ?thir.3 not assigned. could be any value when read. tempty thir.2 transmit fifo empty. a real?time bit that is set high when the fifo is empty. tfull thir.1 transmit fifo full. a real?time bit that is set high when the fifo is full. tudr thir.0 transmit fifo underrun. set when the transmit fifo unwantedly empties out and an abort is automatically sent. note: the tudr bit is latched and will be cleared when read. thfr: transmit hdlc fifo register (address=b7 hex) (msb) (lsb) hdlc7 hdlc6 hdlc5 hdlc4 hdlc3 hdlc2 hdlc1 hdlc0 symbol position name and description hdlc7 thfr.7 hdlc data bit 7. msb of a hdlc packet data byte. hdlc6 thfr.6 hdlc data bit 6. hdlc5 thfr.5 hdlc data bit 5. hdlc4 thfr.4 hdlc data bit 4. hdlc3 thfr.3 hdlc data bit 3. hdlc2 thfr.2 hdlc data bit 2. hdlc1 thfr.1 hdlc data bit 1. hdlc0 thfr.0 hdlc data bit 0. lsb of a hdlc packet data byte.
ds21q44 67 of 105 rdc1: receive hdlc ds0 control register 1 (address=b8 hex) (msb) (lsb) rhs rsads rds0m rd4 rd3 rd2 rd1 rd0 symbol position name and description rhs rdc1.7 receive hdlc source 0 = sa bits defined by rcr2.3 to rcr2.7. 1 = sa bits or ds0 channels defined by rdc1 (see bits defined below). rsads rdc1.6 receive sa bit / ds0 select. 0 = route sa bits to the hdlc controller. rd0 to rd4 defines which sa bits are to be routed. rd4 corresponds to sa4, rd3 to sa5, rd2 to sa6, rd1 to sa7 and rd0 to sa8. 1 = route ds0 channels into the hdlc controller. rdc1.5 is used to determine how the ds0 channels are selected. rds0m rdc1.5 ds0 selection mode. 0 = utilize the rd0 to rd4 bits to select which single ds0 channel to use. 1 = utilize the rchblk control registers to select which ds0 channels to use. rd4 rdc1.4 ds0 channel select bit 4. msb of the ds0 channel select. rd3 rdc1.3 ds0 channel select bit 3. rd2 rdc1.2 ds0 channel select bit 2. rd1 rdc1.1 ds0 channel select bit 1. rd0 rdc1.0 ds0 channel select bit 0. lsb of the ds0 channel select.
ds21q44 68 of 105 rdc2: receive hdlc ds0 control register 2 (address=b9 hex) (msb) (lsb) rdb8 rdb7 rdb6 rdb5 rdb4 rdb3 rdb2 rdb1 symbol position name and description rdb8 rdc2.7 ds0 bit 8 suppress enable. msb of the ds0. set to one to stop this bit from being used. rdb7 rdc2.6 ds0 bit 7 suppress enable. set to one to stop this bit from being used. rdb6 rdc2.5 ds0 bit 6 suppress enable. set to one to stop this bit from being used. rdb5 rdc2.4 ds0 bit 5 suppress enable. set to one to stop this bit from being used. rdb4 rdc2.3 ds0 bit 4 suppress enable. set to one to stop this bit from being used. rdb3 rdc2.2 ds0 bit 3 suppress enable. set to one to stop this bit from being used. rdb2 rdc2.1 ds0 bit 2 suppress enable. set to one to stop this bit from being used. rdb1 rdc2.0 ds0 bit 1 suppress enable. lsb of the ds0. set to one to stop this bit from being used. tdc1: transmit hdlc ds0 control register 1 (address = ba hex) (msb) (lsb) the tsads tds0m td4 td3 td2 td1 td0 symbol position name and description the tdc1.7 transmit hdlc enable. 0 = disable hdlc controller (no data inserted by hdlc controller into the transmit data stream) 1 = enable hdlc controller to allow insertion of hdlc data into either the sa position or multiple ds0 channels as defined by tdc1 (see bit definitions below). tsads tdc1.6 transmit sa bit / ds0 select. this bit is ignored if tdc1.7 is set to zero. 0 = route sa bits from the hdlc controller. td0 to td4 defines which sa bits are to be routed. td4 corresponds to sa4, td3 to sa5, td2 to sa6, td1 to sa7 and td0 to sa8. 1 = route ds0 channels from the hdlc controller. tdc1.5 is used to determine how the ds0 channels are selected.
ds21q44 69 of 105 symbol position name and description tds0m tdc1.5 ds0 selection mode. 0 = utilize the td0 to td4 bits to select which single ds0 channel to use. 1 = utilize the tchblk control registers to select which ds0 channels to use. td4 tdc1.4 ds0 channel select bit 4. msb of the ds0 channel select. td3 tdc1.3 ds0 channel select bit 3. td2 tdc1.2 ds0 channel select bit 2. td1 tdc1.1 ds0 channel select bit 1. td0 tdc1.0 ds0 channel select bit 0. lsb of the ds0 channel select. tdc2: transmit hdlc ds0 control register 2 (address = bb hex) (msb) (lsb) tdb8 tdb7 tdb6 tdb5 tdb4 tdb3 tdb2 tdb1 symbol position name and description tdb8 tdc2.7 ds0 bit 8 suppress enable. msb of the ds0. set to one to stop this bit from being used. tdb7 tdc2.6 ds0 bit 7 suppress enable. set to one to stop this bit from being used. tdb6 tdc2.5 ds0 bit 6 suppress enable. set to one to stop this bit from being used. tdb5 tdc2.4 ds0 bit 5 suppress enable. set to one to stop this bit from being used. tdb4 tdc2.3 ds0 bit 4 suppress enable. set to one to stop this bit from being used. tdb3 tdc2.2 ds0 bit 3 suppress enable. set to one to stop this bit from being used. tdb2 tdc2.1 ds0 bit 2 suppress enable. set to one to stop this bit from being used. tdb1 tdc2.0 ds0 bit 1 suppress enable. lsb of the ds0. set to one to stop this bit from being used. 16. interleaved pcm bus operation in many architectures, the outputs of individual framers are combined into higher speed serial buses to simplify transport across the system. the ds21q44 can be configured to allow each framer?s data and signaling busses to be multiplexed into higher speed data and signaling busses eliminating external hardware saving board space and cost. the interleaved pcm bus option supports two bus speeds and interleave modes. the 4.096 mhz bus speed allows two framers to share a common bus. the 8.192 mhz bus speed allows all four of the ds21q44?s framers to share a common bus. framers can interleave their data either on byte or frame boundaries. framers that share a common bus must be configured through software and require several device pins to be connected together externally (see figures 16-1 & 16-2). each framer?s elastic stores must be enabled and configured for 2.048 mhz operation. the signal rsync must be configured as an input on each framer.
ds21q44 70 of 105 for all bus configurations, one framer will be configured as the master device and the remaining framers on the shared bus will be configured as slave devices. refer to the ibo register description below for more detail. in the 4.096 mhz bus configuration there is one master and one slave per bus. figure 18-1 shows the ds21q44 configured to support two 4.096 mhz buses. bus 1 consists of framers 0 and 1. bus 2 consists of framers 2 and 3. framers 0 and 2 are programmed as master devices. framers 1 and 3 are programmed as slave devices. in the 8.192 mhz bus configuration there is one master and three slaves. figure 18-2 shows the ds21q44 configured to support a 8.192 mhz bus. framer 0 is programmed as the master device. framers 1, 2 and 3 are programmed as slave devices. consult timing diagrams in section 18 for additional information. when using the frame interleave mode, all framers that share an interleaved bus must have receive signals (rpos & rneg) that are synchronous with each other. the received signals must originate from the same clock reference. this restriction does not apply in the byte interleave mode. ibo: interleave bus operation register (address = b5 hex) (msb) (lsb) ????iboenintselmsel0msel1 symbol position name and description ?ibo.7 not assigned. should be set to 0. ?ibo.6 not assigned. should be set to 0. ?ibo.5 not assigned. should be set to 0. ?ibo.4 not assigned. should be set to 0. iboen ibo.3 interleave bus operation enable 0 = interleave bus operation disabled. 1 = interleave bus operation enabled. intsel ibo.2 interleave type select 0 = byte interleave. 1 = frame interleave. msel0 ibo.1 master device bus select bit 0 see table 16-1. msel1 ibo.0 master device bus select bit 1 see table 16-1. master device bus select table 16-1 msel1 msel0 function 0 0 slave device. 0 1 master device with 1 slave device (4.096 mhz bus rate) 1 0 master device with 3 slave devices (8.192 mhz bus rate) 11reserved
ds21q44 71 of 105 4.096 mhz interleaved bus external pin connection example figure 16-1 8.192 mhz interleaved bus external pin connection example figure 16-2 rsysclk0 tsysclk0 rser0 tser0 rsync0 tssync0 rsig0 tsig0 framer 0 rsysclk1 tsysclk1 rser1 tser1 rsync1 tssync1 rsig1 tsig1 framer 1 sysclk sync input rser tser rsig tsig bus 1 bus 2 rsysclk2 tsysclk2 rser2 tser2 rsync2 tssync2 rsig2 tsig2 framer 2 rsysclk3 tsysclk3 rser3 tser3 rsync3 tssync3 rsig3 tsig3 framer 3 sysclk sync input rser tser rsig tsig rsysclk0 tsysclk0 rser0 tser0 rsync0 tssync0 rsig0 tsig0 framer 0 rsysclk1 tsysclk1 rser1 tser1 rsync1 tssync1 rsig1 tsig1 framer 1 rsysclk2 tsysclk2 rser2 tser2 rsync2 tssync2 rsig2 tsig2 framer 2 rsysclk3 tsysclk3 rser3 tser3 rsync3 tssync3 rsig3 tsig3 framer 3 sysclk sync input rser tser rsig tsig
ds21q44 72 of 105 17. jtag-boundary scan architecture and test access port 17.1 description the ds21q44 ieee 1149.1 design supports the standard instruction codes sample/preload, bypass, and extest. optional public instructions included with this design are highz, clamp, and idcode. see figure 17-1 for a block diagram. the ds21q44 contains the following items which meet the requirements set by the ieee 1149.1 standard test access port and boundary scan architecture. test access port (tap) tap controller instruction register bypass register boundary scan register device identification register the jtag feature is only available when the ds21q44 feature set is selected (fms = 0). the jtag feature is disabled when the ds21q44 is configured for emulation of the ds21q43 (fms = 1). details on boundary scan architecture and the test access port can be found in ieee 1149.1-1990, ieee 1149.1a-1993, and ieee 1149.1b-1994. the test access port has the necessary interface pins; jtrst*, jtclk, jtms, jtdi, and jtdo. see the pin descriptions for details. boundary scan architecture figure 17-1 +v boundary scan register identification register bypass register instruction register jtdi jtms jtclk jtrst jtdo +v +v test access port controller mux 10k 10k 10k select output enable
ds21q44 73 of 105 17.2 tap controller state machine this section covers the details on the operation of the test access port (tap) controller state machine. please see figure 17.2 for details on each of the states described below. tap controller the tap controller is a finite state machine that responds to the logic level at jtms on the rising edge of jtclk. test-logic-reset upon power up of the ds21q44, the tap controller will be in the test-logic-reset state. the instruction register will contain the idcode instruction. all system logic of the ds21q44 will operate normally. run-test-idle the run-test-idle is used between scan operations or during specific tests. the instruction register and test registers will remain idle. select-dr-scan all test registers retain their previous state. with jtms low, a rising edge of jtclk moves the controller into the capture-dr state and will initiate a scan sequence. jtms high during a rising edge on jtclk moves the controller to the select-ir capture-dr data may be parallel-loaded into the test data registers selected by the current instruction. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. on the rising edge of jtclk, the controller will go to the shift- dr state if jtms is low or it will go to the exit1-dr state if jtms is high. shift-dr the test data register selected by the current instruction will be connected between jtdi and jtdo and will shift data one stage towards its serial output on each rising edge of jtclk. if a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state. exit1-dr while in this state, a rising edge on jtclk with jtms high will put the controller in the update-dr state, and terminate the scanning process. a rising edge on jtclk with jtms low will put the controller in the pause-dr state. pause-dr shifting of the test registers is halted while in this state. all test registers selected by the current instruction will retain their previous state. the controller will remain in this state while jtms is low. a rising edge on jtclk with jtms high will put the controller in the exit2-dr state.
ds21q44 74 of 105 exit2-dr while in this state, a rising edge on jtclk with jtms high will put the controller in the update-dr state and terminate the scanning process. a rising edge on jtclk with jtms low will enter the shift- dr state. update-dr a falling edge on jtclk while in the update-dr state will latch the data from the shift register path of the test registers into the data output latches. this prevents changes at the parallel output due to changes in the shift register. a rising edge on jtclk with jtms low, will put the controller in the run-test-idle state. with jtms high, the controller will enter the select-dr-scan state. select-ir-scan all test registers retain their previous state. the instruction register will remain unchanged during this state. with jtms low, a rising edge of jtclk moves the controller into the capture-ir state and will initiate a scan sequence for the instruction register. jtms high during a rising edge on jtclk puts the controller back into the test-logic-reset state. capture-ir the capture-ir state is used to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of jtclk. if jtms is high on the rising edge of jtclk, the controller will enter the exit1-ir state. if jtms is low on the rising edge of jtclk, the controller will enter the shift-ir state. shift-ir in this state, the shift register in the instruction register is connected between jtdi and jtdo and shifts data one stage for every rising edge of jtclk towards the serial output. the parallel registers, as well as all test registers remain at their previous states. a rising edge on jtclk with jtms high will move the controller to the exit1-ir state. a rising edge on jtclk with jtms low will keep the controller in the shift-ir state while moving data one stage thorough the instruction shift register. exit1-ir a rising edge on jtclk with jtms low will put the controller in the pause-ir state. if jtms is high on the rising edge of jtclk, the controller will enter the update-ir state and terminate the scanning process. pause-ir shifting of the instruction shift register is halted temporarily. with jtms high, a rising edge on jtclk will put the controller in the exit2-ir state. the controller will remain in the pause-ir state if jtms is low during a rising edge on jtclk. exit2-ir a rising edge on jtclk with jtms low will put the controller in the update-ir state. the controller will loop back to shift-ir if jtms is high during a rising edge of jtclk in this state. update-ir the instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of jtclk as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on jtclk with jtms low, will put the controller in the run-test-idle state. with jtms high, the controller will enter the select-dr-scan state.
ds21q44 75 of 105 tap controller state machine figure 17-2 17.3 instruction register and instructions the instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift-ir state, the instruction shift register will be connected between jtdi and jtdo. while in the shift-ir state, a rising edge on jtclk with jtms low will shift the data one stage towards the serial output at jtdo. a rising edge on jtclk in the exit1-ir state or the exit2- ir state with jtms high will move the controller to the update-ir state the falling edge of that same jtclk will latch the data in the instruction shift register to the instruction parallel output. instructions supported by the ds21q44 with their respective operational binary codes are shown in table 17-1. 1 0 0 1 11 1 1 1 1 1 11 1 1 00 00 0 1 0 0 0 0 1 1 0 0 0 0 select dr-scan capture dr shift dr exit dr pause dr exit2 dr update dr select ir-scan capture ir shift ir exit ir pause ir exit2 ir update ir test logic reset run test/ idle 0
ds21q44 76 of 105 instruction codes for the ds21q44 ieee 1149.1 architecture table 17-1 instruction selected register instruction code sample/preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp boundary scan 011 highz boundary scan 100 idcode device identification 001 sample/preload a mandatory instruction for the ieee 1149.1 specification. this instruction supports two functions. the digital i/os of the ds21q44 can be sampled at the boundary scan register without interfering with the normal operation of the device by using the capture-dr state. sample/preload also allows the ds21q44 to shift data into the boundary scan register via jtdi using the shift-dr state. extest extest allows testing of all interconnections to the ds21q44. when the extest instruction is latched in the instruction register, the following actions occur. once enabled via the update-ir state, the parallel outputs of all digital output pins will be driven. the boundary scan register will be connected between jtdi and jtdo. the capture-dr will sample all digital inputs into the boundary scan register. bypass when the bypass instruction is latched into the parallel instruction register, jtdi connects to jtdo through the one-bit bypass test register. this allows data to pass from jtdi to jtdo not affecting the device?s normal operation. idcode when the idcode instruction is latched into the parallel instruction register, the identification test register is selected. the device identification code will be loaded into the identification register on the rising edge of jtclk following entry into the capture-dr state. shift-dr can be used to shift the identification code out serially via jtdo. during test-logic-reset, the identification code is forced into the instruction register?s parallel output. the id code will always have a ?1? in the lsb position. the next 11 bits identify the manufacturer?s jedec number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. see table 17-2. table 17-3 lists the device id codes for the ds21q42 and ds21q44 devices. id code structure table 17-2 msb lsb contents version (contact factory) device id (see table 17-3) jedec ?00010100001? ?1? length 4 bits 16bits 11bits 1bit
ds21q44 77 of 105 device id codes table 17-3 device 16-bit number ds21q42 0000h ds21q44 0001h high z all digital outputs of the ds21q44 will be placed in a high impedance state. the bypass register will be connected between jtdi and jtdo. clamp all digital outputs of the ds21q44 will output data from the boundary scan parallel output while connecting the bypass register between jtdi and jtdo. the outputs will not change during the clamp instruction. 17.4 test registers ieee 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. an optional test register has been included with the ds21q44 design. this test register is the identification register and is used in conjunction with the idcode instruction and the test-logic-reset state of the tap controller. boundary scan register this register contains both a shift register path and a latched parallel output for all control cells and digital i/o cells and is 126 bits in length. table 17-4 shows all of the cell bit locations and definitions. bypass register this is a single one-bit shift register used in conjunction with the bypass, clamp, and highz instructions, which provides a short path between jtdi and jtdo. identification register the identification register contains a 32-bit shift register and a 32-bit latched parallel output. this register is selected during the idcode instruction and when the tap controller is in the test-logic- reset state. boundary scan register description table 17-4 device pin scan register bit symbol type control bit description 1 81 tchblk0 o 2 80 tpos0 o 3 79 tneg0 o 478 rlink0o 577 rlclk0o 6 76 rclk0 i 7 75 rneg0 i 8 74 rpos0 i
ds21q44 78 of 105 device pin scan register bit symbol type control bit description 973 rsig0o 10 72 rchblk0 o 11 71 rsysclk0 i - 70 rsync0.cntl - 0 = rsync0 an input 1 = rsync0 an output 12 69 rsync0 i/o 13 68 rser0 o 14 - vss - 15 - vdd - 16 67 spare1 - 17 66 rfsync0 o 18 - jtrst* i 19 65 tclk0 i 20 64 tlclk0 o - 63 tsync0.cntl - 0 = tsync0 an input 1 = tsync0 an output 21 62 tsync0 i/o 22 61 tlink0 i 23 60 a0 i 24 59 a1 i 25 58 a2 i 26 57 a3 i 27 56 a4 i 28 55 a5 i 29 54 a6/ale (as) i 30 53 int* o 31 52 tsysclk1 i 32 51 tser1 i 33 50 tssync1 i 34 49 tsig1 i 35 48 tchblk1 o 36 47 tpos1 o 37 46 tneg1 o 38 45 rlink1 o 39 44 rlclk1 o 40 43 rclk1 i 41 42 rneg1 i 42 41 rpos1 i 43 40 rsig1 o 44 39 rchblk1 o 45 38 rsysclk1 i 46 37 a7 i 47 36 fms i
ds21q44 79 of 105 device pin scan register bit symbol type control bit description - 35 rsync1.cntl - 0 = rsync1 an input 1 = rsync1 an output 48 34 rsync1 i/o 49 33 rser1 o 50 - jtms i 51 32 rfsync1 o 52 - jtclk i 53 31 tclk1 i 54 30 tlclk1 o - 29 tsync1.cntl - 0 = tsync1 an input 1 = tsync1 an output 55 28 tsync1 i/o 56 27 tlink1 i 57 26 test i 58 25 fs0 i 59 24 fs1 i 60 23 cs* i 61 22 bts i 62 21 rd*/(ds*) i 63 20 wr*/(r/w*) i 64 19 mux i 65 18 tsysclk2 i 66 17 tser2 i 67 16 tssync2 i 68 15 tsig2 i 69 14 tchblk2 o 70 13 tpos2 o 71 12 tneg2 o 72 11 rlink2 o 73 10 rlclk2 o 74 9 rclk2 i 75 8 rneg2 i 76 7 rpos2 i 77 6 rsig2 o 78 - vss - 79 - vdd - 80 5 rchblk2 o 81 4 rsysclk2 i - 3 rsync2.cntl - 0 = rsync2 an input 1 = rsync2 an output 82 2 rsync2 i/o 83 1 rser2 o 84 - jtdi i 85 0 rfsync2 o
ds21q44 80 of 105 device pin scan register bit symbol type control bit description 86 - jtdo o 87 125 tclk2 i 88 124 tlclk2 o - 123 tsync2.cntl - 0 = tsync2 an input 1 = tsync2 an output 89 122 tsync2 i/o 90 121 tlink2 i 91 120 tsysclk3 i 92 119 tser3 i 93 118 tssync3 i 94 117 tsig3 i 95 116 tchblk3 o 96 115 tpos3 o 97 114 tneg3 o 98 113 rlink3 o 99 112 rlclk3 o 100 111 rclk3 i 101 110 rneg3 i 102 109 rpos3 i 103 108 rsig3 o 104 107 rchblk3 o 105 106 rsysclk3 i - 105 rsync3.cntl - 0 = rsync3 an input 1 = rsync3 an output 106 104 rsync3 i/o 107 103 rser3 o 108 102 8mclk o 109 101 rfsync3 o 110 - vss - 111 - vdd - 112 100 clksi i 113 99 tclk3 i 114 98 tlclk3 o - 97 tsync3.cntl - 0 = tsync3 an input 1 = tsync3 an output 115 96 tsync3 i/o 116 95 tlink3 i - 94 bus.cntl - 0 = d0-d7 or ad0-ad7 are inputs 1 = d0-d7 or ad0-ad7 are outputs 117 93 d0 or ad0 i/o 118 92 d1 or ad1 i/o 119 91 d2 or ad2 i/o
ds21q44 81 of 105 device pin scan register bit symbol type control bit description 120 90 d3 or ad3 i/o 121 89 d4 or ad4 i/o 122 88 d5 or ad5 i/o 123 87 d6 or ad6 i/o 124 86 d7 or ad7 i/o 125 85 tsysclk0 i 126 84 tser0 i 127 83 tssync0 i 128 82 tsig0 i
ds21q44 82 of 105 18. timing diagrams receive side timing figure 18-1 receive side boundary timing (with elastic store disabled) figure 18-2 3 rclk rsync / rfsync rchclk rchblk rlclk rlink 2 notes: 1. there is a 6 rclk delay from rpos, rneg to rser 2. rchblk is programmed to block channel 2 3. rlink is programmed to output the sa4 bit 4. shown is a non-align frame boundary 5. rsig normally contains the cas multiframe alignment nibble (0000) in channel 1 sa4 sa5 sa7 sa8 sa6 lsb msb msb channel 2 rser channel 32 si 1 a sa4 channel 1 sa5 sa6 sa7 sa8 d channel 2 rsig channel 32 channel 1 sa5 a b c note 5 lsb msb channel 2 si 1 a sa4 channel 1 sa5 sa6 sa7 sa8 rpos, rneg 1 lsb 12 345 6 7 8 9 10 11 12 13 14 15 16 frame# 1 12 345 6 14 15 16 2 3 rsync / rfsync rsync rlclk rlink notes: 1. rsync in the frame mode (rcr1.6 = 0) 2. rsync in the multiframe mode (rcr1.6 = 1) 3. rlclk is programmed to output just the sa4 bit 4. rlink will always output all five sa bits as well as the rest of the receive data stream 5. this dia g ram assumes the cas mf be g ins with the fas word 4
ds21q44 83 of 105 receive side 1.544 mhz boundary timing (with elastic store enabled) figure 18-3 receive side 2.048 mhz boundary timing (with elastic store enabled) figure 18-4 rser lsb msb f msb lsb rchclk rsync / rmsync rchblk rsysclk rsync 1 2 3 channel 23/31 channel 24/32 channel 1/2 4 notes: 1. data from the e1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the e1 link is mapped to channel 1 of the t1 link, etc.) and the f-bit position is added (forced to one) 2. rsync is in the output mode (rcr1.5 = 0) 3. rsync is in the input mode (rcr1.5 = 1) 4. rchblk is programmed to block channel 24 rser lsb msb lsb channel 1 rchclk rsync / rmsync rchblk rsysclk rsync channel 31 channel 32 1 2 3 msb notes: 1. rsync is in the output mode (rcr1.5 = 0) 2. rsync is in the input mode (rcr1.5 = 1) 3. rchblk is programmed to block channel 1 4. rsig normally contains the cas multiframe alignment nibble (0000) in channel 1 rsig d channel 1 channel 31 channel 32 note 4 a b c d ab c
ds21q44 84 of 105 receive side interleaved bus operation byte mode timing figure 18-5 rser lsb sysclk rsync framer 3, channel 32 msb lsb framer 0, channel 1 rsig d/b d/b c/d b a c/a b framer 3, channel 32 a framer 0, channel 1 msb lsb framer 1, channel 1 d/b c/d b a framer 1, channel 1 notes: 1. 4.096 mhz bus configuration. 2. 8.192 mhz bus configuration. 3. rsync is in the in p ut mode ( rcr1.5 = 1 ) . 3 rser rsync rsig fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2 rser rsig fr2 ch32 fr3 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 fr2 ch32 fr3 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2 1 1 2 2 bit detail
ds21q44 85 of 105 receive side interleaved bus operation frame mode timing figure 18-6 transmit side timing figure 18-7 12 345 6 7 8 9 10 11 12 13 14 15 16 frame# 1 tsync tsync tlclk tlink 12 345 6 14 15 16 2 3 3 notes: 1. tsync in the frame mode (tcr1.1 = 0) 2. tsync in the multiframe mode (tcr1.1 = 1) 3. tlink is programmed to source just the sa4 bit 4. this diagram assumes both the cas mf and the crc4 begin with the align frame transmit side timing figure 13.5 rser lsb sysclk rsync framer 3, channel 32 msb lsb framer 0, channel 1 rsig d/b d/b c/d b a c/a b framer 3, channel 32 a framer 0, channel 1 msb lsb framer 0, channel 2 d/b c/d b a framer 0, channel 2 notes: 1. 4.096 mhz bus configuration. 2. 8.192 mhz bus configuration. 3. rsync is in the in p ut mode ( rcr1.5 = 1 ) . 3 rser rsync rsig fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 rser rsig fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 1 1 2 2 bit detail
ds21q44 86 of 105 transmit side boundary timing (with elastic store disabled) figure 18-8 transmit side 1.544 mhz boundary timing (with elastic store enabled) figure 18-9 lsb msb channel 2 channel 1 tchclk 2 3 tclk tsync tsync tchblk 4 don't care tlclk tlink don't care 5 5 a sa4 sa5 sa6 sa7 sa8 notes: 1. there is a 5 tclk delay from tser to tpos and tneg 2. tsync is in the input mode (tcr1.0 = 0) 3. tsync is in the output mode (tcr1.0 = 1) 4. tchblk is programmed to block channel 2 5. tlink is programmed to source the sa4 bits 6. the signaling data at tsig during channel 1 is normally overwritten in the transmit formatter with the cas multiframe alignment nibble (0000) 7. shown is a non-align frame boundary tpos, tneg si 1 channel 2 channel 1 tsig b cd a bcd note 6 lsb msb lsb msb a sa4 sa5 sa6 sa7 sa8 tser si 1 channel 1 msb channel 32 1 tser lsb msb lsb channel 1 tchclk tchblk tsysclk tssync channel 23 channel 24 notes: 1. tchblk is programmed to block channel 23 2. the f-bit position is ignored by the ds2154 1 msb f-bit
ds21q44 87 of 105 transmit side 2.048 mhz boundary timing (with elastic store enabled) figure 18-10 g.802 timing figure 18-11 tser lsb msb lsb channel 1 tchclk tchblk tsysclk tssync channel 31 channel 32 notes: 1. tchblk is programmed to block channel 31 tsig dd channel 1 channel 31 channel 32 c b a c b a 1 msb a lsb msb timeslot 25 timeslot 26 1 1 0 2345678910 31 30 timeslot # 11 1213 1415 16 18 17 19 2021 2223 2425 2627 2829 3031 0 1 2 3 4 rchclk/tchclk rchblk/tchblk rser/tser rchclk/tchclk rchblk/tchblk rclk / rsysclk tclk / tsysclk rsync/tsync notes: 1. rchblk or tchblk is programmed to pulse high during timeslots 1 to 15, 17 to 25, and during bit 1 of timeslot 26 detail g.802 timing figure 13.9
ds21q44 88 of 105 transmit side interleaved bus operation byte mode timing figure 18-12 tser lsb sysclk tssync framer 3, channel 32 msb lsb framer 0, channel 1 tsig d/b d/b c/d b a c/a b framer 3, channel 32 a framer 0, channel 1 msb lsb framer 1, channel 1 d/b c/d b a framer 1, channel 1 notes: 1. 4.096 mhz bus configuration. 2. 8.192 mhz bus confi g uration. tser tssync tsig tser tsig fr2 ch32 fr3 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 fr2 ch32 fr3 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 1 1 2 2 bit detail fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2 fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2
ds21q44 89 of 105 transmit side interleaved bus operation frame mode timing figure 18-13 tser lsb sysclk tssync framer 3, channel 32 msb lsb framer 0, channel 1 tsig d/b d/b c/d b a c/a b framer 3, channel 32 a framer 0, channel 1 msb lsb framer 0, channel 2 d/b c/d b a framer 0, channel 2 notes: 1. 4.096 mhz bus configuration. 2. 8.192 mhz bus confi g uration. tser tssync tsig fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 tser tsig fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 1 1 2 2 bit detail
ds21q44 90 of 105 ds21q44 framer synchronization flowchart figure 18-14 fas resync criteria met check for >=915 out of 1000 crc4 word errors 8ms time out rlos = 1 set fasrc (rir.1) cas resync criteria met; set casrc (rir.0) fas search fassa = 1 fas sync criteria met fassa = 0 cas sync criteria met cassa = 0 if crc4 is on (ccr1.0 = 1) rlos = 1 if cas is on (ccr1.3 = 0) power up increment crc4 sync counter; crc4sa = 0 crc4 resync criteria met (rir.2) cas multiframe search (if enabled via ccr1.3) cassa = 1 crc4 multiframe search (if enabled via ccr1.0) crc4sa = 1 resync if rcr1.0 = 0 check for fas framing error (depends on rcr1.2) check for cas mf word error sync declared rlos = 0 crc4 sync criteria met; crc4sa = 0; reset crc4 sync counter
ds21q44 91 of 105 ds21q44 transmit data flow figure 18-15 si bit inserti on control (tcr1.3) ti mesl ot 0 pass-through (tcr1. 6) e-bi t generation (tcr2.1) sa bit insertion control (tcr2.3 thru tcr2.7) idle code / channel insertion control via tir1/2/3/4 transmit unframed all ones (tcr1. 4) or auto ais (ccr2.5) code wor d gener at i on crc4 enable (ccr1.4) taf tnaf.5-7 tlink ts1 to ts16 ti dr tpos, tneg 0 1 0 1 1 0 01 1 0 01 01 1 0 ais generation transmi t signaling all ones (tcr1. 2) = register = device pi n = selector key: tcbr1/2/3/4 rser (note #1) ccr3. 6 tcr1.5 signaling bit insertion control tir function select (ccr3.5) ais generation 01 notes: 1. tclk should be tied to rclk and tsync should be tied to rfsync for data to be properly sourced from rser. 2. auto remote alarm if enabled will only overwrite bit 3 of timeslot 0 in the not align frames if the alarm needs to be sent. sa bi t inserti on control regi ster (tsacr) 1 0 tsa4 to tsa8 tra tsi naf tsiaf crc4 mul t i f r ame al i gnment word generation (ccr.4) receive si de crc4 error detector 01 auto remote alarm generation (ccr2.4) per-channel code generation (tcc1/2/3/4) 01 tc1 t o tc32 hdlc engi ne ds0 data source mux (tdc1/2) 01 tser & tdata taf/tnaf bi t mux 0 1 tnaf.0-4 sa data source mux (tdc1) 0 1 ds0 monitor tsig hardware signaling insertion 01 tcbr1/2/3/4 ccr3. 5 ccr3. 2
ds21q44 92 of 105 19. operating parameters absolute maximum ratings* voltage on any non-supply pin relative to ground ?1.0v to +5.5v supply voltage ?.3v to +3.63v operating temperature for ds21q44t 0oc to 70oc operating temperature for DS21Q44TN ?40oc to +85oc storage temperature ?55oc to +125oc * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0oc to 70oc for ds21q44t; 0oc to +85oc for DS21Q44TN) parameter symbol min typ max units notes logic 1 v ih 2.0 5.5 v logic 0 v il ?0.3 +0.8 v supply v dd 2.97 3.63 v capacitance (t a =25oc) parameter symbol min typ max units notes input capacitance c in 5pf output capacitance c out 7pf dc characteristics (0oc to 70oc; v dd = 2.97 to 3.63v for ds21q44t; -40oc to +85oc; v dd = 2.97 to 3.63v for DS21Q44TN) parameter symbol min typ max units notes supply current @ 3.3v i dd 75 ma 1 input leakage i il ?1.0 +1.0 a 2 output leakage i lo 1.0 a 3 output current (2.4v) i oh ?1.0 ma output current (0.4v) i ol +4.0 ma notes: 1. tclk=rclk=tsysclk=rsysclk=2.048 mhz; outputs open circuited. 2. 0.0v < v in < v dd . 3. applied to int* when 3?stated.
ds21q44 93 of 105 ac characteristics ? multiplexed parallel port (mux=1) (0oc to 70oc; v dd = 2.97 to 3.63v for ds21q44t ?40oc to +85oc; v dd = 2.97 to 3.63v for DS21Q44TN) parameter symbol min typ max units notes cycle time t cyc 200 ns pulse width, ds low or rd* high pw el 100 ns pulse width, ds high or rd* low pw eh 100 ns input rise/fall times t r , t f 20 ns r/w* hold time t rwh 10 ns r/w* set up time before ds high t rws 50 ns cs*, fso or fs1 set up time before ds, wr* or rd* active t cs 20 ns cs*, fso or fs1 hold time t ch 0ns read data hold time t dhr 10 50 ns write data hold time t dhw 0ns muxed address valid to as or ale fall t asl 15 ns muxed address hold time t ahl 10 ns delay time ds, wr* or rd* to as or ale rise t asd 20 ns pulse width as or ale high pw ash 30 ns delay time, as or ale to ds, wr* or rd* t ased 10 ns output data delay time from ds or rd* t ddr 20 80 ns data set up time t dsw 50 ns see figures 19-1 to 19-3 for details.
ds21q44 94 of 105 ac characteristics ? non?multiplexed parallel port (mux=0 ) (0oc to 70oc; v dd = 2.97 to 3.63v for ds21q44t; ?40oc to +85oc; v dd = 2.97 to 3.63v for DS21Q44TN) parameter symbol min typ max units notes set up time for a0 to a7, fs0 or fs1 valid to cs* active t 1 0ns set up time for cs* active to either rd*, wr*, or ds* active t 2 0ns delay time from either rd* or ds* active to data valid t 3 75 ns hold time from either rd*, wr*, or ds* inactive to cs* inactive t 4 0ns hold time from cs* inactive to data bus 3? state t 5 520ns wait time from either wr* or ds* active to latch data t 6 75 ns data set up time to either wr* or ds* inactive t 7 10 ns data hold time from either wr* or ds* inactive t 8 10 ns address hold from either wr* or ds* inactive t 9 10 ns see figures 19?4 to 19?7 for details.
ds21q44 95 of 105 ac characteristics ? receive side (0oc to 70oc; v dd = 2.97 to 3.63v for ds21q44t; ?40oc to +85oc; v dd = 2.97 to 3.63v for DS21Q44TN) parameter symbol min typ max units notes rclk period t cp 488 ns rclk pulse width t ch t cl 75 75 ns ns rsysclk period t sp t sp 122 122 648 488 ns ns 1 2 rsysclk pulse width t sh t sl 50 50 ns ns rsync set up to rsysclk falling t su 20 t sh ?5 ns rsync pulse width t pw 50 ns rpos/rneg set up to rclk falling t su 20 ns rpos/rneg hold from rclk falling t hd 20 ns rsysclk/rclki rise and fall times t r , t f 25 ns delay rclk to rser, rsig, rlink valid t d1 50 ns delay rclk to rchclk, rsync, rchblk, rfsync, rlclk t d2 50 ns delay rsysclk to rser, rsig valid t d3 50 ns delay rsysclk to rchclk, rchblk, rmsync, rsync t d4 50 ns see figures 19-8 to 18-10 for details. notes: 1. rsysclk = 1.544 mhz. 2. rsysclk = 2.048 mhz.
ds21q44 96 of 105 ac characteristics ? transmit side (0oc to 70oc; v dd = 2.97 to 3.63v for ds21q44t; ?40oc to +85oc; ; v dd = 2.97 to 3.63v for DS21Q44TN) parameter symbol min typ max units notes tclk period t cp 488 ns tclk pulse width t ch t cl 75 75 ns ns tclki pulse width t lh t ll 75 75 ns ns tsysclk period t sp t sp 122 122 648 448 ns ns 1 2 tsysclk pulse width t sh t sl 50 50 ns ns tsync or tssync set up to tclk or tsysclk falling t su 20 t ch ?5 or t sh ?5 ns tsync or tssync pulse width t pw 50 ns tser, tsig, tlink set up to tclk, tsysclk falling t su 20 ns tser, tsig, tlink hold from tclk, tsysclk falling t hd 20 ns tclk or tsysclk rise and fall times t r , t f 25 ns delay tclk to tpos, tneg valid t dd 50 ns delay tclk to tchblk, tchblk, tsync, tlclk t d2 50 ns delay tsysclk to tchclk, tchblk t d3 75 ns see figures 19?11 to 19?13 for details. notes: 1. tsysclk = 1.544 mhz. 2. tsysclk = 2.048 mhz.
ds21q44 97 of 105 intel bus read ac timing (bts=0 / mux = 1) figure 19-1 intel bus write timing (bts=0 / mux=1) figure 19-2 ash pw t cyc t asd t asd pw pw eh el t t t t t t a hl ch cs asl ased cs* ad0-ad7 dhr t ddr ale rd* wr* ash pw t cyc t asd t asd pw pw eh el t t t t t t t a hl dsw dhw ch cs asl ased cs* ad0-ad7 rd* wr* ale
ds21q44 98 of 105 motorola bus ac timing (bts = 1 / mux = 1) figure 19-3 intel bus read ac timing (bts=0 / mux=0) figure 19-4 t asd ash pw t t asl ahl t cs t asl t t t dsw dhw t ch t t t ddr dhr rwh t ased pw eh t rws a hl pw el t cyc as ds ad0-ad7 (write) ad0-ad7 (read) r/w* cs* a ddress valid data valid a 0 to a7, fs0, fs1 d0 to d7 wr* cs* rd* 0ns min. 0ns min. 75ns max. 0ns min. 5ns min. / 20ns max. t1 t2 t3 t4 t5
ds21q44 99 of 105 intel bus write ac timing (bts=0 / mux=0) figure 19-5 motorola bus read ac timing (bts=1 / mux=0) figure 19-6 a ddress valid a 0 to a7, fs0, fs1 d0 to d7 rd* cs* wr* 0ns min. 0ns min. 75ns min. 0ns min. 10ns min. 10ns min. t1 t2 t6 t4 t7 t8 a ddress valid data valid a 0 to a7, fs0, fs1 d0 to d7 r/w* cs* ds* 0ns min. 0ns min. 75ns max. 0ns min. 5ns min. / 20ns max. motorola bus read ac timing (bts = 1 / mux = 0) figure 16.12 t1 t2 t3 t4 t5 ds 0ns min. 75ns max. 0ns min. t2 t3 t4 1 notes: 1. the signal ds is active high when emulating the ds21q43 (fms = 1) .
ds21q44 100 of 105 motorola bus write ac timing (bts=1 / mux=0) figure 19-7 address valid a0 to a7, fs0 , fs1 d0 to d7 r/w* cs* ds* 0ns min. 0ns min. 75ns min. 0ns min. 10ns min. 10ns min. t1 t2 t6 t4 t7 t8 ds 0ns min. 75ns min. 1 notes: 1. the signal ds is active high when emulating the ds21q43 (fms = 1) . t2 t6
ds21q44 101 of 105 receive side ac timing figure 19-8 t d1 1 t d2 t d2 t d2 t d2 rser / rsig rchclk rchblk rsync rlclk rlink t d1 notes: 1. rsync is in the output mode (rcr1.5 = 0). 2. rlclk will only pulse high during sa bit locations as defined in rcr2; no relationship between rlclk and rsync or rfsync is implied. rclk receive side ac timing figure 14.4 t d2 rfsync / rmsync msb of channel 1 2 sa4 to sa8 bit position
ds21q44 102 of 105 receive system side ac timing figure 19-9 t f t r t d3 1 t d4 t d4 t d4 t t su hd 2 rser / rsig rchclk rchblk rsync rsync notes: 1. rsync i s i n the out put mode ( rcr1.5 = 0) 2. rsync i s i n the i nput mode (rcr1.5 = 1) rsysclk sl t t sp sh t t d4 rmsync msb of channel 1 receive line interface ac timing figure 19-10 t f t r rpos, rneg rclk cl t t cp ch t t su t hd
ds21q44 103 of 105 transmit side ac timing figure 19-11 t f t r 1 tclk tser / tsig tchclk t t cl t ch cp tsync tsync tlink tlclk tchblk t d2 t d2 t d2 t t t t t hd su d2 su hd t hd 2 notes: 1. tsync is in the output mode (tcr1.0 = 1). 2. tsync is in the input mode (tcr1.0 = 0). 3. tser is sampled on the falling edge of tclk when the transmit side elastic store is disabled. 4. tchclk and tchblk are synchronous with tclk when the transmit side elastic store is disabled. 5. tlink is only sampled during sa bit locations as defined in tcr2; no relationship between tlclk/tlink and tsync is implied. 5 t su
ds21q44 104 of 105 transmit system side ac timing figure 19-12 t f t r tsysclk tser tchclk t t sl t sh sp tssync tchblk t d3 t d3 t t t su hd su t hd notes: 1. tser is onl y sampled on the falli ng edge of tsysclk when the tr ansmit si de el asti c store is enabled. 2. tchclk and tchblk are synchronous wi th tsysclk when t he transmi t si de el asti c store i s enabl ed. transmit line interface side ac timing figure 19-13 t f t r tclk tpos, tneg t t cl t ch cp t dd
ds21q44 105 of 105 20. 128-pin tqfp package specifications

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